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spi: Fix typo in devicetree/bindings/spi

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This patch fix spelling typos found in
Documentation/devicetree/bingings/spi.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Masanari Iida 2016-06-29 04:33:33 +09:00 committed by Mark Brown
parent 1a695a905c
commit 0fb7620fba
2 changed files with 2 additions and 2 deletions
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2
Documentation/devicetree/bindings/spi/spi-davinci.txt
View File

@ -21,7 +21,7 @@ Required properties:
IP to the interrupt controller within the SoC. Possible values
are 0 and 1. Manual says one of the two possible interrupt
lines can be tied to the interrupt controller. Set this
based on a specifc SoC configuration.
based on a specific SoC configuration.
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle

2
Documentation/devicetree/bindings/spi/ti_qspi.txt
View File

@ -20,7 +20,7 @@ Optional properties:
chipselect register and offset of that register.
NOTE: TI QSPI controller requires different pinmux and IODelay
paramaters for Mode-0 and Mode-3 operations, which needs to be set up by
parameters for Mode-0 and Mode-3 operations, which needs to be set up by
the bootloader (U-Boot). Default configuration only supports Mode-0
operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
specified in the slave nodes of TI QSPI controller without appropriate