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[media] atmel-isi: prepare for the support of preview path
Atmel ISI support a preview path which can output RGB data. So this patch introduces a bool variable to choose which path is enabled currently. And also we need setup corresponding path registers. By default the preview path is disabled. We only use Codec path. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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@ -79,6 +79,7 @@ struct atmel_isi {
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dma_addr_t fb_descriptors_phys;
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struct list_head dma_desc_head;
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struct isi_dma_desc dma_desc[MAX_BUFFER_NUM];
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bool enable_preview_path;
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struct completion complete;
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/* ISI peripherial clock */
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@ -195,11 +196,19 @@ static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
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/* start next dma frame. */
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isi->active = list_entry(isi->video_buffer_list.next,
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struct frame_buffer, list);
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isi_writel(isi, ISI_DMA_C_DSCR,
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(u32)isi->active->p_dma_desc->fbd_phys);
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isi_writel(isi, ISI_DMA_C_CTRL,
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ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
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isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
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if (!isi->enable_preview_path) {
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isi_writel(isi, ISI_DMA_C_DSCR,
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(u32)isi->active->p_dma_desc->fbd_phys);
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isi_writel(isi, ISI_DMA_C_CTRL,
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ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
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isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
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} else {
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isi_writel(isi, ISI_DMA_P_DSCR,
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(u32)isi->active->p_dma_desc->fbd_phys);
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isi_writel(isi, ISI_DMA_P_CTRL,
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ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
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isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_P_CH);
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}
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}
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return IRQ_HANDLED;
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}
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@ -226,7 +235,8 @@ static irqreturn_t isi_interrupt(int irq, void *dev_id)
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isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
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ret = IRQ_HANDLED;
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} else {
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if (likely(pending & ISI_SR_CXFR_DONE))
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if (likely(pending & ISI_SR_CXFR_DONE) ||
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likely(pending & ISI_SR_PXFR_DONE))
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ret = atmel_isi_handle_streaming(isi);
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}
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@ -371,21 +381,35 @@ static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
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ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
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/* Check if already in a frame */
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if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
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dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n");
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return;
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}
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if (!isi->enable_preview_path) {
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if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
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dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n");
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return;
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}
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isi_writel(isi, ISI_DMA_C_DSCR, (u32)buffer->p_dma_desc->fbd_phys);
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isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
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isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
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isi_writel(isi, ISI_DMA_C_DSCR,
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(u32)buffer->p_dma_desc->fbd_phys);
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isi_writel(isi, ISI_DMA_C_CTRL,
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ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
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isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
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} else {
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isi_writel(isi, ISI_DMA_P_DSCR,
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(u32)buffer->p_dma_desc->fbd_phys);
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isi_writel(isi, ISI_DMA_P_CTRL,
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ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
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isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_P_CH);
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}
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cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK;
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/* Enable linked list */
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cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR;
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/* Enable codec path and ISI */
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ctrl = ISI_CTRL_CDC | ISI_CTRL_EN;
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/* Enable ISI */
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ctrl = ISI_CTRL_EN;
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if (!isi->enable_preview_path)
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ctrl |= ISI_CTRL_CDC;
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isi_writel(isi, ISI_CTRL, ctrl);
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isi_writel(isi, ISI_CFG1, cfg1);
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}
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@ -462,15 +486,17 @@ static void stop_streaming(struct vb2_queue *vq)
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}
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spin_unlock_irq(&isi->lock);
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timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
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/* Wait until the end of the current frame. */
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while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
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time_before(jiffies, timeout))
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msleep(1);
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if (!isi->enable_preview_path) {
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timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
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/* Wait until the end of the current frame. */
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while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
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time_before(jiffies, timeout))
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msleep(1);
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if (time_after(jiffies, timeout))
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dev_err(icd->parent,
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"Timeout waiting for finishing codec request\n");
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if (time_after(jiffies, timeout))
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dev_err(icd->parent,
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"Timeout waiting for finishing codec request\n");
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}
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/* Disable interrupts */
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isi_writel(isi, ISI_INTDIS,
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