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RISC-V: Initial DTS for Microchip ICICLE board
Add initial DTS for Microchip ICICLE board having only essential devices (clocks, sdhci, ethernet, serial, etc). The device tree is based on the U-Boot patch. https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Atish Patra
Palmer Dabbelt
parent
d53b0244c8
commit
0fa6107eca
@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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subdir-y += sifive
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subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
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subdir-y += microchip
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obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
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2
arch/riscv/boot/dts/microchip/Makefile
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2
arch/riscv/boot/dts/microchip/Makefile
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
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72
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
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72
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
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@ -0,0 +1,72 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 Microchip Technology Inc */
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/dts-v1/;
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#include "microchip-mpfs.dtsi"
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/* Clock frequency (in Hz) of the rtcclk */
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#define RTCCLK_FREQ 1000000
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip PolarFire-SoC Icicle Kit";
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compatible = "microchip,mpfs-icicle-kit";
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chosen {
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stdout-path = &serial0;
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};
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cpus {
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timebase-frequency = <RTCCLK_FREQ>;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x40000000>;
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clocks = <&clkcfg 26>;
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};
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soc {
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};
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&serial2 {
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status = "okay";
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};
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&serial3 {
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status = "okay";
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};
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&sdcard {
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status = "okay";
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};
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&emac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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phy0: ethernet-phy@8 {
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reg = <8>;
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ti,fifo-depth = <0x01>;
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};
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};
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&emac1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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phy1: ethernet-phy@9 {
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reg = <9>;
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ti,fifo-depth = <0x01>;
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};
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};
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329
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
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329
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
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@ -0,0 +1,329 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 Microchip Technology Inc */
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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model = "Microchip MPFS Icicle Kit";
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compatible = "microchip,mpfs-icicle-kit";
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chosen {
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@1 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@2 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@3 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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cpu@4 {
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clock-frequency = <0>;
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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d-cache-size = <32768>;
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d-tlb-sets = <1>;
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d-tlb-size = <32>;
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device_type = "cpu";
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <32768>;
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i-tlb-sets = <1>;
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i-tlb-size = <32>;
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mmu-type = "riscv,sv39";
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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status = "okay";
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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cache-size = <2097152>;
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <1 2 3>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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};
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clint@2000000 {
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compatible = "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0xC000>;
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7>;
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};
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plic: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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compatible = "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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riscv,ndev = <186>;
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 11
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&cpu1_intc 11 &cpu1_intc 9
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&cpu2_intc 11 &cpu2_intc 9
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&cpu3_intc 11 &cpu3_intc 9
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&cpu4_intc 11 &cpu4_intc 9>;
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};
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dma@3000000 {
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compatible = "sifive,fu540-c000-pdma";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <23 24 25 26 27 28 29 30>;
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#dma-cells = <1>;
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};
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refclk: refclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <600000000>;
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clock-output-names = "msspllclk";
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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reg-names = "mss_sysreg";
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clocks = <&refclk>;
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#clock-cells = <1>;
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clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
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"mac0", "mac1", "mmc", "timer", /* 4-7 */
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"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
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"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
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"i2c1", "can0", "can1", "usb", /* 16-19 */
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"rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
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"gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
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"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
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};
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serial0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <90>;
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current-speed = <115200>;
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clocks = <&clkcfg 8>;
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status = "disabled";
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};
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serial1: serial@20100000 {
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compatible = "ns16550a";
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reg = <0x0 0x20100000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <91>;
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current-speed = <115200>;
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clocks = <&clkcfg 9>;
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status = "disabled";
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};
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serial2: serial@20102000 {
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compatible = "ns16550a";
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reg = <0x0 0x20102000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <92>;
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current-speed = <115200>;
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clocks = <&clkcfg 10>;
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status = "disabled";
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};
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serial3: serial@20104000 {
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compatible = "ns16550a";
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reg = <0x0 0x20104000 0x0 0x400>;
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reg-io-width = <4>;
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reg-shift = <2>;
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interrupt-parent = <&plic>;
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interrupts = <93>;
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current-speed = <115200>;
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clocks = <&clkcfg 11>;
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status = "disabled";
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};
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emmc: mmc@20008000 {
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compatible = "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <88 89>;
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pinctrl-names = "default";
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clocks = <&clkcfg 6>;
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bus-width = <4>;
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cap-mmc-highspeed;
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mmc-ddr-3_3v;
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max-frequency = <200000000>;
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non-removable;
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no-sd;
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no-sdio;
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voltage-ranges = <3300 3300>;
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status = "disabled";
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};
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sdcard: sdhc@20008000 {
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compatible = "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <88>;
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pinctrl-names = "default";
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clocks = <&clkcfg 6>;
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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max-frequency = <200000000>;
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status = "disabled";
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};
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emac0: ethernet@20110000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <64 65 66 67>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg 4>, <&clkcfg 2>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emac1: ethernet@20112000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <70 71 72 73>;
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mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg 5>, <&clkcfg 2>;
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status = "disabled";
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clock-names = "pclk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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