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pwm: lpc18xx-sct: Test clock rate to avoid division by 0

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The clk API may return 0 on clk_get_rate(), so we should check the
result before using it as a divisor.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Wolfram Sang 2016-03-02 23:57:09 +01:00 committed by Thierry Reding
parent bea307c16a
commit 0e47b5981a
1 changed files with 5 additions and 0 deletions
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5
drivers/pwm/pwm-lpc18xx-sct.c
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@ -360,6 +360,11 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev)
}
lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
if (!lpc18xx_pwm->clk_rate) {
dev_err(&pdev->dev, "pwm clock has no frequency\n");
ret = -EINVAL;
goto disable_pwmclk;
}
mutex_init(&lpc18xx_pwm->res_lock);
mutex_init(&lpc18xx_pwm->period_lock);