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Blackfin arch: cleanup cache lock code

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- remove cheesy read_iloc() function
 - move invalidate_entire_icache function to lock.S
 - export proper prototypes for functions in lock.S
 - only build lock.S when BFIN_ICACHE_LOCK is enabled

Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Mike Frysinger 2008-08-14 14:29:57 +08:00 committed by Bryan Wu
parent 55546ac45d
commit 0e06b50dda
4 changed files with 39 additions and 17 deletions
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2
arch/blackfin/kernel/setup.c
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@ -1059,7 +1059,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
BFIN_DLINES);
#ifdef CONFIG_BFIN_ICACHE_LOCK
switch (read_iloc()) {
switch ((bfin_read_IMEM_CONTROL() >> 3) & WAYALL_L) {
case WAY0_L:
seq_printf(m, "Way0 Locked-Down\n");
break;

3
arch/blackfin/mach-common/Makefile
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@ -4,8 +4,9 @@
obj-y := \
cache.o entry.o head.o \
interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
interrupt.o irqpanic.o arch_checks.o ints-priority.o
obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
obj-$(CONFIG_PM) += pm.o dpmc_modes.o
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o

45
arch/blackfin/mach-common/lock.S
View File

@ -28,13 +28,10 @@
*/
#include <linux/linkage.h>
#include <asm/cplb.h>
#include <asm/blackfin.h>
.text
#ifdef CONFIG_BFIN_ICACHE_LOCK
/* When you come here, it is assumed that
* R0 - Which way to be locked
*/
@ -189,18 +186,38 @@ ENTRY(_cache_lock)
RTS;
ENDPROC(_cache_lock)
#endif /* BFIN_ICACHE_LOCK */
/* Return the ILOC bits of IMEM_CONTROL
/* Invalidate the Entire Instruction cache by
* disabling IMC bit
*/
ENTRY(_invalidate_entire_icache)
[--SP] = ( R7:5);
ENTRY(_read_iloc)
P1.H = HI(IMEM_CONTROL);
P1.L = LO(IMEM_CONTROL);
R1 = 0xF;
R0 = [P1];
R0 = R0 >> 3;
R0 = R0 & R1;
P0.L = LO(IMEM_CONTROL);
P0.H = HI(IMEM_CONTROL);
R7 = [P0];
/* Clear the IMC bit , All valid bits in the instruction
* cache are set to the invalid state
*/
BITCLR(R7,IMC_P);
CLI R6;
SSYNC; /* SSYNC required before invalidating cache. */
.align 8;
[P0] = R7;
SSYNC;
STI R6;
/* Configures the instruction cache agian */
R6 = (IMC | ENICPLB);
R7 = R7 | R6;
CLI R6;
SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
.align 8;
[P0] = R7;
SSYNC;
STI R6;
( R7:5) = [SP++];
RTS;
ENDPROC(_read_iloc)
ENDPROC(_invalidate_entire_icache)

6
include/asm-blackfin/bfin-global.h
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@ -62,7 +62,6 @@ extern void _cplb_hdr(void);
/* Blackfin cache functions */
extern void bfin_icache_init(void);
extern void bfin_dcache_init(void);
extern int read_iloc(void);
extern int bfin_console_init(void);
extern asmlinkage void lower_to_irq14(void);
extern asmlinkage void bfin_return_from_exception(void);
@ -126,6 +125,11 @@ extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
/* only used when CONFIG_MTD_UCLINUX */
extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
#ifdef CONFIG_BFIN_ICACHE_LOCK
extern void cache_grab_lock(int way);
extern void cache_lock(int way);
#endif
#endif
#endif /* _BLACKFIN_H_ */