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sh: Provide optimized non-atomic bitops for SH-2A.
This ties in the new SH-2A 32-bit non-atomic bitops. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
8bcc5c1c33
commit
0d5bbe0bc2
142
arch/sh/include/asm/bitops-op32.h
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142
arch/sh/include/asm/bitops-op32.h
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@ -0,0 +1,142 @@
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#ifndef __ASM_SH_BITOPS_OP32_H
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#define __ASM_SH_BITOPS_OP32_H
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/*
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* The bit modifying instructions on SH-2A are only capable of working
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* with a 3-bit immediate, which signifies the shift position for the bit
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* being worked on.
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*/
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#if defined(__BIG_ENDIAN)
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#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
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#define BYTE_NUMBER(nr) ((nr ^ BITOP_LE_SWIZZLE) / BITS_PER_BYTE)
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#define BYTE_OFFSET(nr) ((nr ^ BITOP_LE_SWIZZLE) % BITS_PER_BYTE)
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#else
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#define BYTE_NUMBER(nr) ((nr) / BITS_PER_BYTE)
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#define BYTE_OFFSET(nr) ((nr) % BITS_PER_BYTE)
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#endif
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#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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__asm__ __volatile__ (
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"bset.b %1, @(%O2,%0) ! __set_bit\n\t"
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: "+r" (addr)
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: "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr))
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: "t", "memory"
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);
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} else {
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p |= mask;
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}
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}
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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__asm__ __volatile__ (
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"bclr.b %1, @(%O2,%0) ! __clear_bit\n\t"
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: "+r" (addr)
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: "i" (BYTE_OFFSET(nr)),
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"i" (BYTE_NUMBER(nr))
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: "t", "memory"
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);
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} else {
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p &= ~mask;
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}
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}
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/**
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* __change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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{
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if (IS_IMMEDIATE(nr)) {
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__asm__ __volatile__ (
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"bxor.b %1, @(%O2,%0) ! __change_bit\n\t"
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: "+r" (addr)
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: "i" (BYTE_OFFSET(nr)),
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"i" (BYTE_NUMBER(nr))
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: "t", "memory"
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);
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} else {
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p ^= mask;
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}
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}
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/**
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* __test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old | mask;
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return (old & mask) != 0;
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}
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/**
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* __test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old & ~mask;
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return (old & mask) != 0;
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}
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/* WARNING: non atomic and it can be reordered! */
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static inline int __test_and_change_bit(int nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old ^ mask;
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return (old & mask) != 0;
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}
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/**
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* test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static inline int test_bit(int nr, const volatile unsigned long *addr)
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{
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return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
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}
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#endif /* __ASM_SH_BITOPS_OP32_H */
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@ -13,6 +13,9 @@
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#ifdef CONFIG_GUSA_RB
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#include <asm/bitops-grb.h>
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#elif defined(CONFIG_CPU_SH2A)
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#include <asm-generic/bitops/atomic.h>
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#include <asm/bitops-op32.h>
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#elif defined(CONFIG_CPU_SH4A)
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#include <asm/bitops-llsc.h>
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#else
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