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ARM: io: RiscPC: eliminate private inb() et.al. definitions
As we've got rid of the bit-31 set IO addresses, we can now use the standard inb() definitions and reduce the IO space limit to 64K. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
5e4cdb83ed
commit
0d26449dd6
@ -15,192 +15,18 @@
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#include <mach/hardware.h>
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#define IO_SPACE_LIMIT 0xffffffff
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#define IO_SPACE_LIMIT 0xffff
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/*
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* We use two different types of addressing - PC style addresses, and ARM
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* addresses. PC style accesses the PC hardware with the normal PC IO
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* addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+
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* and are translated to the start of IO. Note that all addresses are
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* shifted left!
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*/
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#define __PORT_PCIO(x) (!((x) & 0x80000000))
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/*
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* Dynamic IO functions.
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*/
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static inline void __outb (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"strb %1, [%0, %2, lsl #2] @ outb"
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: "=&r" (temp)
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: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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static inline void __outw (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"str %1, [%0, %2, lsl #2] @ outw"
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: "=&r" (temp)
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: "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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static inline void __outl (unsigned int value, unsigned int port)
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{
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unsigned long temp;
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__asm__ __volatile__(
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"tst %2, #0x80000000\n\t"
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"mov %0, %4\n\t"
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"addeq %0, %0, %3\n\t"
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"str %1, [%0, %2, lsl #2] @ outl"
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: "=&r" (temp)
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: "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
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: "cc");
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}
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#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
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static inline unsigned sz __in##fnsuffix (unsigned int port) \
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{ \
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unsigned long temp, value; \
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__asm__ __volatile__( \
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"tst %2, #0x80000000\n\t" \
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"mov %0, %4\n\t" \
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"addeq %0, %0, %3\n\t" \
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"ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \
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: "=&r" (temp), "=r" (value) \
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: "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
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: "cc"); \
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return (unsigned sz)value; \
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}
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static inline void __iomem *__deprecated __ioaddr(unsigned int port)
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{
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void __iomem *ret;
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if (__PORT_PCIO(port))
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ret = PCIO_BASE;
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else
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ret = IO_BASE;
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return ret + (port << 2);
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}
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#define DECLARE_IO(sz,fnsuffix,instr) \
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DECLARE_DYN_IN(sz,fnsuffix,instr)
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DECLARE_IO(char,b,"b")
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DECLARE_IO(short,w,"")
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DECLARE_IO(int,l,"")
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#undef DECLARE_IO
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#undef DECLARE_DYN_IN
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/*
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* Constant address IO functions
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* We need PC style IO addressing for:
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* - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7)
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* - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a)
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* - 8250 serial (only for compile)
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*
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* These have to be macros for the 'J' constraint to work -
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* +/-4096 immediate operand.
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* These peripherals are found in an area of MMIO which looks very much
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* like an ISA bus, but with registers at the low byte of each word.
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*/
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#define __outbc(value,port) \
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({ \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"strb %0, [%1, %2] @ outbc" \
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: : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inbc(port) \
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({ \
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unsigned char result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldrb %0, [%1, %2] @ inbc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result; \
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})
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#define __outwc(value,port) \
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({ \
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unsigned long __v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outwc" \
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: : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outwc" \
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: : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inwc(port) \
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({ \
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unsigned short result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inwc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inwc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result & 0xffff; \
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})
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#define __outlc(value,port) \
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({ \
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unsigned long __v = value; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"str %0, [%1, %2] @ outlc" \
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: : "r" (__v), "r" (IO_BASE), "r" ((port) << 2)); \
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})
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#define __inlc(port) \
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({ \
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unsigned long result; \
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if (__PORT_PCIO((port))) \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \
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else \
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__asm__ __volatile__( \
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"ldr %0, [%1, %2] @ inlc" \
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: "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \
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result; \
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})
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#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
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#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
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#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
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#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
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#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
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#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
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#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
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#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
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#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
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#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
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#define __io(a) (PCIO_BASE + ((a) << 2))
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/*
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* 1:1 mapping for ioremapped regions.
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