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[ARM] 3284/1: S3C2400 - adds support to GPIO
Patch from Lucas Correia Villa Real This patch adds support to GPIO on the S3C2400, which is going to be used by the GP32 machine and the SMDK2400 development board. Signed-off-by: Lucas Correia Villa Real <lucasvr@gobolinux.org> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lucas Correia Villa Real
Russell King
parent
7610dfa372
commit
0ca5bc3de7
@ -10,9 +10,13 @@ obj-m :=
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obj-n :=
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obj- :=
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# S3C2400 support files
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obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o
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# S3C2410 support files
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obj-$(CONFIG_CPU_S3C2410) += s3c2410.o
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obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o
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obj-$(CONFIG_S3C2410_DMA) += dma.o
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# Power Management support
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@ -25,6 +29,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
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obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o
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# bast extras
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@ -31,6 +31,7 @@
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* 05-Nov-2004 BJD EXPORT_SYMBOL() added for all code
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* 13-Mar-2005 BJD Updates for __iomem
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* 26-Oct-2005 BJD Added generic configuration types
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* 15-Jan-2006 LCVR Added support for the S3C2400
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*/
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@ -48,7 +49,7 @@
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void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
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{
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void __iomem *base = S3C2410_GPIO_BASE(pin);
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void __iomem *base = S3C24XX_GPIO_BASE(pin);
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unsigned long mask;
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unsigned long con;
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unsigned long flags;
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@ -95,7 +96,7 @@ EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
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unsigned int s3c2410_gpio_getcfg(unsigned int pin)
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{
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void __iomem *base = S3C2410_GPIO_BASE(pin);
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void __iomem *base = S3C24XX_GPIO_BASE(pin);
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unsigned long mask;
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if (pin < S3C2410_GPIO_BANKB) {
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@ -111,7 +112,7 @@ EXPORT_SYMBOL(s3c2410_gpio_getcfg);
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void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
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{
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void __iomem *base = S3C2410_GPIO_BASE(pin);
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void __iomem *base = S3C24XX_GPIO_BASE(pin);
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unsigned long offs = S3C2410_GPIO_OFFSET(pin);
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unsigned long flags;
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unsigned long up;
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@ -133,7 +134,7 @@ EXPORT_SYMBOL(s3c2410_gpio_pullup);
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void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
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{
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void __iomem *base = S3C2410_GPIO_BASE(pin);
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void __iomem *base = S3C24XX_GPIO_BASE(pin);
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unsigned long offs = S3C2410_GPIO_OFFSET(pin);
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unsigned long flags;
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unsigned long dat;
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@ -152,7 +153,7 @@ EXPORT_SYMBOL(s3c2410_gpio_setpin);
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unsigned int s3c2410_gpio_getpin(unsigned int pin)
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{
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void __iomem *base = S3C2410_GPIO_BASE(pin);
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void __iomem *base = S3C24XX_GPIO_BASE(pin);
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unsigned long offs = S3C2410_GPIO_OFFSET(pin);
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return __raw_readl(base + 0x04) & (1<< offs);
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@ -166,70 +167,13 @@ unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
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unsigned long misccr;
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local_irq_save(flags);
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misccr = __raw_readl(S3C2410_MISCCR);
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misccr = __raw_readl(S3C24XX_MISCCR);
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misccr &= ~clear;
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misccr ^= change;
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__raw_writel(misccr, S3C2410_MISCCR);
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__raw_writel(misccr, S3C24XX_MISCCR);
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local_irq_restore(flags);
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return misccr;
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}
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EXPORT_SYMBOL(s3c2410_modify_misccr);
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int s3c2410_gpio_getirq(unsigned int pin)
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{
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if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
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return -1; /* not valid interrupts */
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if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
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return -1; /* not valid pin */
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if (pin < S3C2410_GPF4)
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return (pin - S3C2410_GPF0) + IRQ_EINT0;
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if (pin < S3C2410_GPG0)
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return (pin - S3C2410_GPF4) + IRQ_EINT4;
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return (pin - S3C2410_GPG0) + IRQ_EINT8;
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}
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EXPORT_SYMBOL(s3c2410_gpio_getirq);
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int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
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unsigned int config)
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{
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void __iomem *reg = S3C2410_EINFLT0;
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unsigned long flags;
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unsigned long val;
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if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
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return -1;
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config &= 0xff;
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pin -= S3C2410_GPG8_EINT16;
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reg += pin & ~3;
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local_irq_save(flags);
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/* update filter width and clock source */
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val = __raw_readl(reg);
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val &= ~(0xff << ((pin & 3) * 8));
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val |= config << ((pin & 3) * 8);
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__raw_writel(val, reg);
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/* update filter enable */
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val = __raw_readl(S3C2410_EXTINT2);
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val &= ~(1 << ((pin * 4) + 3));
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val |= on << ((pin * 4) + 3);
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__raw_writel(val, S3C2410_EXTINT2);
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
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45
arch/arm/mach-s3c2410/s3c2400-gpio.c
Normal file
45
arch/arm/mach-s3c2410/s3c2400-gpio.c
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@ -0,0 +1,45 @@
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/* linux/arch/arm/mach-s3c2410/gpio.c
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*
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* Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
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*
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* S3C2400 GPIO support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Changelog
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* 15-Jan-2006 LCVR Splitted from gpio.c, adding support for the S3C2400
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/arch/regs-gpio.h>
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int s3c2400_gpio_getirq(unsigned int pin)
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{
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if (pin < S3C2410_GPE0 || pin > S3C2400_GPE7_EINT7)
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return -1; /* not valid interrupts */
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return (pin - S3C2410_GPE0) + IRQ_EINT0;
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}
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EXPORT_SYMBOL(s3c2400_gpio_getirq);
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93
arch/arm/mach-s3c2410/s3c2410-gpio.c
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93
arch/arm/mach-s3c2410/s3c2410-gpio.c
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@ -0,0 +1,93 @@
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/* linux/arch/arm/mach-s3c2410/gpio.c
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*
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* Copyright (c) 2004-2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2410 GPIO support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Changelog
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* 15-Jan-2006 LCVR Splitted from gpio.c
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/arch/regs-gpio.h>
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int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
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unsigned int config)
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{
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void __iomem *reg = S3C2410_EINFLT0;
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unsigned long flags;
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unsigned long val;
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if (pin < S3C2410_GPG8 || pin > S3C2410_GPG15)
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return -1;
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config &= 0xff;
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pin -= S3C2410_GPG8_EINT16;
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reg += pin & ~3;
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local_irq_save(flags);
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/* update filter width and clock source */
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val = __raw_readl(reg);
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val &= ~(0xff << ((pin & 3) * 8));
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val |= config << ((pin & 3) * 8);
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__raw_writel(val, reg);
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/* update filter enable */
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val = __raw_readl(S3C2410_EXTINT2);
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val &= ~(1 << ((pin * 4) + 3));
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val |= on << ((pin * 4) + 3);
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__raw_writel(val, S3C2410_EXTINT2);
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(s3c2410_gpio_irqfilter);
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int s3c2410_gpio_getirq(unsigned int pin)
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{
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if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15_EINT23)
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return -1; /* not valid interrupts */
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if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
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return -1; /* not valid pin */
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if (pin < S3C2410_GPF4)
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return (pin - S3C2410_GPF0) + IRQ_EINT0;
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if (pin < S3C2410_GPG0)
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return (pin - S3C2410_GPF4) + IRQ_EINT4;
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return (pin - S3C2410_GPG0) + IRQ_EINT8;
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}
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EXPORT_SYMBOL(s3c2410_gpio_getirq);
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@ -72,7 +72,7 @@ ENTRY(s3c2410_cpu_suspend)
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@@ prepare cpu to sleep
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ldr r4, =S3C2410_REFRESH
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ldr r5, =S3C2410_MISCCR
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ldr r5, =S3C24XX_MISCCR
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ldr r6, =S3C2410_CLKCON
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ldr r7, [ r4 ] @ get REFRESH (and ensure in TLB)
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ldr r8, [ r5 ] @ get MISCCR (and ensure in TLB)
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@ -17,6 +17,7 @@
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* 14-Sep-2004 BJD Added misccr and getpin to gpio
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* 01-Oct-2004 BJD Added the new gpio functions
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* 16-Oct-2004 BJD Removed the clock variables
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* 15-Jan-2006 LCVR Added s3c2400_gpio_getirq()
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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@ -55,6 +56,12 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
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extern int s3c2410_gpio_getirq(unsigned int pin);
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#ifdef CONFIG_CPU_S3C2400
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extern int s3c2400_gpio_getirq(unsigned int pin);
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#endif /* CONFIG_CPU_S3C2400 */
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/* s3c2410_gpio_irqfilter
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*
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* set the irq filtering on the given pin
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@ -22,6 +22,7 @@
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* 28-Mar-2005 LCVR Fixed definition of GPB10
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* 26-Oct-2005 BJD Added generic configuration types
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* 27-Nov-2005 LCVR Added definitions to S3C2400 registers
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* 15-Jan-2006 LCVR Written S3C24XX_GPIO_BASE() macro
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*/
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@ -39,6 +40,27 @@
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#define S3C2410_GPIO_BANKG (32*6)
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#define S3C2410_GPIO_BANKH (32*7)
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#ifdef CONFIG_CPU_S3C2400
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#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
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#define S3C24XX_MISCCR S3C2400_MISCCR
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#else
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#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
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#define S3C24XX_MISCCR S3C2410_MISCCR
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#endif /* CONFIG_CPU_S3C2400 */
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/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
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#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
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#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
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#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
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(2 * (S3C2400_BANKNUM(pin)-2)))
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#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
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S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
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S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
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#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
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#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
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