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MIPS: cpu: Convert MIPS_CPU_* defs to (1ull << x)
The MIPS_CPU_* definitions have now filled the first 32-bits, and are getting longer since they're written in hex without zero padding. Adding my 8 extra MIPS_CPU_* definitions which I haven't upstreamed yet this is getting increasingly ugly as the comments get shifted progressively to the right. Its also error prone, and I've seen this cause mistakes on 3 separate occasions now, not helped by it being a conflict hotspot. Convert all the MIPS_CPU_* definitions to the form (1ull << x). Humans are better at incrementing than shifting. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10045/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
James Hogan
Ralf Baechle
parent
c0291f7c73
commit
0c94fa33b4
@ -349,50 +349,57 @@ enum cpu_type_enum {
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MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
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MIPS_CPU_ISA_M64R6)
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/*
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* Private version of BIT_ULL() to escape include file recursion hell.
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* We soon will have to switch to another mechanism that will work with
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* more than 64 bits anyway.
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*/
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#define MBIT_ULL(bit) (1ULL << (bit))
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/*
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* CPU Option encodings
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*/
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#define MIPS_CPU_TLB 0x00000001ull /* CPU has TLB */
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#define MIPS_CPU_4KEX 0x00000002ull /* "R4K" exception model */
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#define MIPS_CPU_3K_CACHE 0x00000004ull /* R3000-style caches */
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#define MIPS_CPU_4K_CACHE 0x00000008ull /* R4000-style caches */
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#define MIPS_CPU_TX39_CACHE 0x00000010ull /* TX3900-style caches */
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#define MIPS_CPU_FPU 0x00000020ull /* CPU has FPU */
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#define MIPS_CPU_32FPR 0x00000040ull /* 32 dbl. prec. FP registers */
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#define MIPS_CPU_COUNTER 0x00000080ull /* Cycle count/compare */
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#define MIPS_CPU_WATCH 0x00000100ull /* watchpoint registers */
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#define MIPS_CPU_DIVEC 0x00000200ull /* dedicated interrupt vector */
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#define MIPS_CPU_VCE 0x00000400ull /* virt. coherence conflict possible */
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#define MIPS_CPU_CACHE_CDEX_P 0x00000800ull /* Create_Dirty_Exclusive CACHE op */
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#define MIPS_CPU_CACHE_CDEX_S 0x00001000ull /* ... same for seconary cache ... */
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#define MIPS_CPU_MCHECK 0x00002000ull /* Machine check exception */
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#define MIPS_CPU_EJTAG 0x00004000ull /* EJTAG exception */
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#define MIPS_CPU_NOFPUEX 0x00008000ull /* no FPU exception */
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#define MIPS_CPU_LLSC 0x00010000ull /* CPU has ll/sc instructions */
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#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000ull /* P-cache subset enforced */
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#define MIPS_CPU_PREFETCH 0x00040000ull /* CPU has usable prefetch */
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#define MIPS_CPU_VINT 0x00080000ull /* CPU supports MIPSR2 vectored interrupts */
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#define MIPS_CPU_VEIC 0x00100000ull /* CPU supports MIPSR2 external interrupt controller mode */
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#define MIPS_CPU_ULRI 0x00200000ull /* CPU has ULRI feature */
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#define MIPS_CPU_PCI 0x00400000ull /* CPU has Perf Ctr Int indicator */
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#define MIPS_CPU_RIXI 0x00800000ull /* CPU has TLB Read/eXec Inhibit */
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#define MIPS_CPU_MICROMIPS 0x01000000ull /* CPU has microMIPS capability */
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#define MIPS_CPU_TLBINV 0x02000000ull /* CPU supports TLBINV/F */
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#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
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#define MIPS_CPU_EVA 0x08000000ull /* CPU supports Enhanced Virtual Addressing */
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#define MIPS_CPU_HTW 0x10000000ull /* CPU support Hardware Page Table Walker */
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#define MIPS_CPU_RIXIEX 0x20000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
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#define MIPS_CPU_MAAR 0x40000000ull /* MAAR(I) registers are present */
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#define MIPS_CPU_FRE 0x80000000ull /* FRE & UFE bits implemented */
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#define MIPS_CPU_RW_LLB 0x100000000ull /* LLADDR/LLB writes are allowed */
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#define MIPS_CPU_XPA 0x200000000ull /* CPU supports Extended Physical Addressing */
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#define MIPS_CPU_CDMM 0x400000000ull /* CPU has Common Device Memory Map */
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#define MIPS_CPU_BP_GHIST 0x8000000000ull /* R12K+ Branch Prediction Global History */
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#define MIPS_CPU_SP 0x10000000000ull /* Small (1KB) page support */
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#define MIPS_CPU_FTLB 0x20000000000ull /* CPU has Fixed-page-size TLB */
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#define MIPS_CPU_NAN_LEGACY 0x40000000000ull /* Legacy NaN implemented */
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#define MIPS_CPU_NAN_2008 0x80000000000ull /* 2008 NaN implemented */
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#define MIPS_CPU_VP 0x100000000000ull /* MIPSr6 Virtual Processors (multi-threading) */
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#define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
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#define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
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#define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
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#define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
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#define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
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#define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
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#define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
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#define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
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#define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
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#define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
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#define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
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#define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
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#define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
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#define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
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#define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
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#define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
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#define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
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#define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
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#define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
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#define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
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#define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
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#define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
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#define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
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#define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
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#define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
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#define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
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#define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
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#define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
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#define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
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#define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
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#define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
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#define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
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#define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
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#define MIPS_CPU_XPA MBIT_ULL(33) /* CPU supports Extended Physical Addressing */
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#define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
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#define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
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#define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
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#define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
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#define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
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#define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
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#define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
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/*
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* CPU ASE encodings
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