Merge branch 'clk-msm8996' into clk-next

* clk-msm8996:
  clk: qcom: Add MSM8996 Multimedia Clock Controller (MMCC) driver
  clk: qcom: Add gfx3d ping-pong PLL frequency switching
  clk: qcom: Add MSM8996 Global Clock Control (GCC) driver
  clk: qcom: Add Alpha PLL support
  clk: divider: Cap table divider values to 'width' member
This commit is contained in:
Stephen Boyd 2015-12-01 00:00:48 -08:00
commit 0b9ddcc84e
13 changed files with 7790 additions and 4 deletions

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@ -13,6 +13,7 @@ Required properties :
"qcom,gcc-msm8974"
"qcom,gcc-msm8974pro"
"qcom,gcc-msm8974pro-ac"
"qcom,gcc-msm8996"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1

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@ -9,6 +9,7 @@ Required properties :
"qcom,mmcc-msm8660"
"qcom,mmcc-msm8960"
"qcom,mmcc-msm8974"
"qcom,mmcc-msm8996"
- reg : shall contain base register location and length
- #clock-cells : shall contain 1

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@ -32,13 +32,14 @@
#define div_mask(width) ((1 << (width)) - 1)
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
u8 width)
{
unsigned int maxdiv = 0;
unsigned int maxdiv = 0, mask = div_mask(width);
const struct clk_div_table *clkt;
for (clkt = table; clkt->div; clkt++)
if (clkt->div > maxdiv)
if (clkt->div > maxdiv && clkt->val <= mask)
maxdiv = clkt->div;
return maxdiv;
}
@ -62,7 +63,7 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
if (flags & CLK_DIVIDER_POWER_OF_TWO)
return 1 << div_mask(width);
if (table)
return _get_table_maxdiv(table);
return _get_table_maxdiv(table, width);
return div_mask(width) + 1;
}

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@ -106,3 +106,20 @@ config MSM_MMCC_8974
Support for the multimedia clock controller on msm8974 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
config MSM_GCC_8996
tristate "MSM8996 Global Clock Controller"
depends on COMMON_CLK_QCOM
help
Support for the global clock controller on msm8996 devices.
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, UFS, SD/eMMC, PCIe, etc.
config MSM_MMCC_8996
tristate "MSM8996 Multimedia Clock Controller"
select MSM_GCC_8996
depends on COMMON_CLK_QCOM
help
Support for the multimedia clock controller on msm8996 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.

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@ -2,6 +2,7 @@ obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
clk-qcom-y += common.o
clk-qcom-y += clk-regmap.o
clk-qcom-y += clk-alpha-pll.o
clk-qcom-y += clk-pll.o
clk-qcom-y += clk-rcg.o
clk-qcom-y += clk-rcg2.o
@ -20,5 +21,7 @@ obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o
obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o

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@ -0,0 +1,355 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/export.h>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include "clk-alpha-pll.h"
#define PLL_MODE 0x00
# define PLL_OUTCTRL BIT(0)
# define PLL_BYPASSNL BIT(1)
# define PLL_RESET_N BIT(2)
# define PLL_LOCK_COUNT_SHIFT 8
# define PLL_LOCK_COUNT_MASK 0x3f
# define PLL_BIAS_COUNT_SHIFT 14
# define PLL_BIAS_COUNT_MASK 0x3f
# define PLL_VOTE_FSM_ENA BIT(20)
# define PLL_VOTE_FSM_RESET BIT(21)
# define PLL_ACTIVE_FLAG BIT(30)
# define PLL_LOCK_DET BIT(31)
#define PLL_L_VAL 0x04
#define PLL_ALPHA_VAL 0x08
#define PLL_ALPHA_VAL_U 0x0c
#define PLL_USER_CTL 0x10
# define PLL_POST_DIV_SHIFT 8
# define PLL_POST_DIV_MASK 0xf
# define PLL_ALPHA_EN BIT(24)
# define PLL_VCO_SHIFT 20
# define PLL_VCO_MASK 0x3
#define PLL_USER_CTL_U 0x14
#define PLL_CONFIG_CTL 0x18
#define PLL_TEST_CTL 0x1c
#define PLL_TEST_CTL_U 0x20
#define PLL_STATUS 0x24
/*
* Even though 40 bits are present, use only 32 for ease of calculation.
*/
#define ALPHA_REG_BITWIDTH 40
#define ALPHA_BITWIDTH 32
#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll, clkr)
#define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll_postdiv, clkr)
static int wait_for_pll(struct clk_alpha_pll *pll)
{
u32 val, mask, off;
int count;
int ret;
const char *name = clk_hw_get_name(&pll->clkr.hw);
off = pll->offset;
ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
if (ret)
return ret;
if (val & PLL_VOTE_FSM_ENA)
mask = PLL_ACTIVE_FLAG;
else
mask = PLL_LOCK_DET;
/* Wait for pll to enable. */
for (count = 100; count > 0; count--) {
ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
if (ret)
return ret;
if ((val & mask) == mask)
return 0;
udelay(1);
}
WARN(1, "%s didn't enable after voting for it!\n", name);
return -ETIMEDOUT;
}
static int clk_alpha_pll_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, mask, off;
off = pll->offset;
mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
if (ret)
return ret;
/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll(pll);
}
/* Skip if already enabled */
if ((val & mask) == mask)
return 0;
ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
PLL_BYPASSNL, PLL_BYPASSNL);
if (ret)
return ret;
/*
* H/W requires a 5us delay between disabling the bypass and
* de-asserting the reset.
*/
mb();
udelay(5);
ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
ret = wait_for_pll(pll);
if (ret)
return ret;
ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
PLL_OUTCTRL, PLL_OUTCTRL);
/* Ensure that the write above goes through before returning. */
mb();
return ret;
}
static void clk_alpha_pll_disable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 val, mask, off;
off = pll->offset;
ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
if (ret)
return;
/* If in FSM mode, just unvote it */
if (val & PLL_VOTE_FSM_ENA) {
clk_disable_regmap(hw);
return;
}
mask = PLL_OUTCTRL;
regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
/* Delay of 2 output clock ticks required until output is disabled */
mb();
udelay(1);
mask = PLL_RESET_N | PLL_BYPASSNL;
regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
}
static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
{
return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
}
static unsigned long
alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
{
u64 remainder;
u64 quotient;
quotient = rate;
remainder = do_div(quotient, prate);
*l = quotient;
if (!remainder) {
*a = 0;
return rate;
}
/* Upper ALPHA_BITWIDTH bits of Alpha */
quotient = remainder << ALPHA_BITWIDTH;
remainder = do_div(quotient, prate);
if (remainder)
quotient++;
*a = quotient;
return alpha_pll_calc_rate(prate, *l, *a);
}
static const struct pll_vco *
alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
{
const struct pll_vco *v = pll->vco_table;
const struct pll_vco *end = v + pll->num_vco;
for (; v < end; v++)
if (rate >= v->min_freq && rate <= v->max_freq)
return v;
return NULL;
}
static unsigned long
clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
u32 l, low, high, ctl;
u64 a = 0, prate = parent_rate;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 off = pll->offset;
regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
if (ctl & PLL_ALPHA_EN) {
regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, &high);
a = (u64)high << 32 | low;
a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
}
return alpha_pll_calc_rate(prate, l, a);
}
static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
const struct pll_vco *vco;
u32 l, off = pll->offset;
u64 a;
rate = alpha_pll_round_rate(rate, prate, &l, &a);
vco = alpha_pll_find_vco(pll, rate);
if (!vco) {
pr_err("alpha pll not in a valid vco range\n");
return -EINVAL;
}
a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);
regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
PLL_VCO_MASK << PLL_VCO_SHIFT,
vco->val << PLL_VCO_SHIFT);
regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
PLL_ALPHA_EN);
return 0;
}
static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l;
u64 a;
unsigned long min_freq, max_freq;
rate = alpha_pll_round_rate(rate, *prate, &l, &a);
if (alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
return clamp(rate, min_freq, max_freq);
}
const struct clk_ops clk_alpha_pll_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_alpha_pll_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
static unsigned long
clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 ctl;
regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
ctl >>= PLL_POST_DIV_SHIFT;
ctl &= PLL_POST_DIV_MASK;
return parent_rate >> fls(ctl);
}
static const struct clk_div_table clk_alpha_div_table[] = {
{ 0x0, 1 },
{ 0x1, 2 },
{ 0x3, 4 },
{ 0x7, 8 },
{ 0xf, 16 },
{ }
};
static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
pll->width, CLK_DIVIDER_POWER_OF_TWO);
}
static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
int div;
/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
div << PLL_POST_DIV_SHIFT);
}
const struct clk_ops clk_alpha_pll_postdiv_ops = {
.recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
.round_rate = clk_alpha_pll_postdiv_round_rate,
.set_rate = clk_alpha_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);

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@ -0,0 +1,57 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __QCOM_CLK_ALPHA_PLL_H__
#define __QCOM_CLK_ALPHA_PLL_H__
#include <linux/clk-provider.h>
#include "clk-regmap.h"
struct pll_vco {
unsigned long min_freq;
unsigned long max_freq;
u32 val;
};
/**
* struct clk_alpha_pll - phase locked loop (PLL)
* @offset: base address of registers
* @vco_table: array of VCO settings
* @clkr: regmap clock handle
*/
struct clk_alpha_pll {
u32 offset;
const struct pll_vco *vco_table;
size_t num_vco;
struct clk_regmap clkr;
};
/**
* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
* @offset: base address of registers
* @width: width of post-divider
* @clkr: regmap clock handle
*/
struct clk_alpha_pll_postdiv {
u32 offset;
u8 width;
struct clk_regmap clkr;
};
extern const struct clk_ops clk_alpha_pll_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
#endif

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@ -178,5 +178,6 @@ extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;
extern const struct clk_ops clk_byte2_ops;
extern const struct clk_ops clk_pixel_ops;
extern const struct clk_ops clk_gfx3d_ops;
#endif

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@ -723,3 +723,90 @@ const struct clk_ops clk_pixel_ops = {
.determine_rate = clk_pixel_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_pixel_ops);
static int clk_gfx3d_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct clk_rate_request parent_req = { };
struct clk_hw *p2, *p8, *p9, *xo;
unsigned long p9_rate;
int ret;
xo = clk_hw_get_parent_by_index(hw, 0);
if (req->rate == clk_hw_get_rate(xo)) {
req->best_parent_hw = xo;
return 0;
}
p9 = clk_hw_get_parent_by_index(hw, 2);
p2 = clk_hw_get_parent_by_index(hw, 3);
p8 = clk_hw_get_parent_by_index(hw, 4);
/* PLL9 is a fixed rate PLL */
p9_rate = clk_hw_get_rate(p9);
parent_req.rate = req->rate = min(req->rate, p9_rate);
if (req->rate == p9_rate) {
req->rate = req->best_parent_rate = p9_rate;
req->best_parent_hw = p9;
return 0;
}
if (req->best_parent_hw == p9) {
/* Are we going back to a previously used rate? */
if (clk_hw_get_rate(p8) == req->rate)
req->best_parent_hw = p8;
else
req->best_parent_hw = p2;
} else if (req->best_parent_hw == p8) {
req->best_parent_hw = p2;
} else {
req->best_parent_hw = p8;
}
ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
if (ret)
return ret;
req->rate = req->best_parent_rate = parent_req.rate;
return 0;
}
static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate, u8 index)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 cfg;
int ret;
/* Just mux it, we don't use the division or m/n hardware */
cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
if (ret)
return ret;
return update_config(rcg);
}
static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
/*
* We should never get here; clk_gfx3d_determine_rate() should always
* make us use a different parent than what we're currently using, so
* clk_gfx3d_set_rate_and_parent() should always be called.
*/
return 0;
}
const struct clk_ops clk_gfx3d_ops = {
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
.recalc_rate = clk_rcg2_recalc_rate,
.set_rate = clk_gfx3d_set_rate,
.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
.determine_rate = clk_gfx3d_determine_rate,
};
EXPORT_SYMBOL_GPL(clk_gfx3d_ops);

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,339 @@
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H
#define _DT_BINDINGS_CLK_MSM_GCC_8996_H
#define GPLL0_EARLY 0
#define GPLL0 1
#define GPLL1_EARLY 2
#define GPLL1 3
#define GPLL2_EARLY 4
#define GPLL2 5
#define GPLL3_EARLY 6
#define GPLL3 7
#define GPLL4_EARLY 8
#define GPLL4 9
#define SYSTEM_NOC_CLK_SRC 10
#define CONFIG_NOC_CLK_SRC 11
#define PERIPH_NOC_CLK_SRC 12
#define MMSS_BIMC_GFX_CLK_SRC 13
#define USB30_MASTER_CLK_SRC 14
#define USB30_MOCK_UTMI_CLK_SRC 15
#define USB3_PHY_AUX_CLK_SRC 16
#define USB20_MASTER_CLK_SRC 17
#define USB20_MOCK_UTMI_CLK_SRC 18
#define SDCC1_APPS_CLK_SRC 19
#define SDCC1_ICE_CORE_CLK_SRC 20
#define SDCC2_APPS_CLK_SRC 21
#define SDCC3_APPS_CLK_SRC 22
#define SDCC4_APPS_CLK_SRC 23
#define BLSP1_QUP1_SPI_APPS_CLK_SRC 24
#define BLSP1_QUP1_I2C_APPS_CLK_SRC 25
#define BLSP1_UART1_APPS_CLK_SRC 26
#define BLSP1_QUP2_SPI_APPS_CLK_SRC 27
#define BLSP1_QUP2_I2C_APPS_CLK_SRC 28
#define BLSP1_UART2_APPS_CLK_SRC 29
#define BLSP1_QUP3_SPI_APPS_CLK_SRC 30
#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
#define BLSP1_UART3_APPS_CLK_SRC 32
#define BLSP1_QUP4_SPI_APPS_CLK_SRC 33
#define BLSP1_QUP4_I2C_APPS_CLK_SRC 34
#define BLSP1_UART4_APPS_CLK_SRC 35
#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
#define BLSP1_QUP5_I2C_APPS_CLK_SRC 37
#define BLSP1_UART5_APPS_CLK_SRC 38
#define BLSP1_QUP6_SPI_APPS_CLK_SRC 39
#define BLSP1_QUP6_I2C_APPS_CLK_SRC 40
#define BLSP1_UART6_APPS_CLK_SRC 41
#define BLSP2_QUP1_SPI_APPS_CLK_SRC 42
#define BLSP2_QUP1_I2C_APPS_CLK_SRC 43
#define BLSP2_UART1_APPS_CLK_SRC 44
#define BLSP2_QUP2_SPI_APPS_CLK_SRC 45
#define BLSP2_QUP2_I2C_APPS_CLK_SRC 46
#define BLSP2_UART2_APPS_CLK_SRC 47
#define BLSP2_QUP3_SPI_APPS_CLK_SRC 48
#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
#define BLSP2_UART3_APPS_CLK_SRC 50
#define BLSP2_QUP4_SPI_APPS_CLK_SRC 51
#define BLSP2_QUP4_I2C_APPS_CLK_SRC 52
#define BLSP2_UART4_APPS_CLK_SRC 53
#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
#define BLSP2_QUP5_I2C_APPS_CLK_SRC 55
#define BLSP2_UART5_APPS_CLK_SRC 56
#define BLSP2_QUP6_SPI_APPS_CLK_SRC 57
#define BLSP2_QUP6_I2C_APPS_CLK_SRC 58
#define BLSP2_UART6_APPS_CLK_SRC 59
#define PDM2_CLK_SRC 60
#define TSIF_REF_CLK_SRC 61
#define CE1_CLK_SRC 62
#define GCC_SLEEP_CLK_SRC 63
#define BIMC_CLK_SRC 64
#define HMSS_AHB_CLK_SRC 65
#define BIMC_HMSS_AXI_CLK_SRC 66
#define HMSS_RBCPR_CLK_SRC 67
#define HMSS_GPLL0_CLK_SRC 68
#define GP1_CLK_SRC 69
#define GP2_CLK_SRC 70
#define GP3_CLK_SRC 71
#define PCIE_AUX_CLK_SRC 72
#define UFS_AXI_CLK_SRC 73
#define UFS_ICE_CORE_CLK_SRC 74
#define QSPI_SER_CLK_SRC 75
#define GCC_SYS_NOC_AXI_CLK 76
#define GCC_SYS_NOC_HMSS_AHB_CLK 77
#define GCC_SNOC_CNOC_AHB_CLK 78
#define GCC_SNOC_PNOC_AHB_CLK 79
#define GCC_SYS_NOC_AT_CLK 80
#define GCC_SYS_NOC_USB3_AXI_CLK 81
#define GCC_SYS_NOC_UFS_AXI_CLK 82
#define GCC_CFG_NOC_AHB_CLK 83
#define GCC_PERIPH_NOC_AHB_CLK 84
#define GCC_PERIPH_NOC_USB20_AHB_CLK 85
#define GCC_TIC_CLK 86
#define GCC_IMEM_AXI_CLK 87
#define GCC_MMSS_SYS_NOC_AXI_CLK 88
#define GCC_MMSS_NOC_CFG_AHB_CLK 89
#define GCC_MMSS_BIMC_GFX_CLK 90
#define GCC_USB30_MASTER_CLK 91
#define GCC_USB30_SLEEP_CLK 92
#define GCC_USB30_MOCK_UTMI_CLK 93
#define GCC_USB3_PHY_AUX_CLK 94
#define GCC_USB3_PHY_PIPE_CLK 95
#define GCC_USB20_MASTER_CLK 96
#define GCC_USB20_SLEEP_CLK 97
#define GCC_USB20_MOCK_UTMI_CLK 98
#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
#define GCC_SDCC1_APPS_CLK 100
#define GCC_SDCC1_AHB_CLK 101
#define GCC_SDCC1_ICE_CORE_CLK 102
#define GCC_SDCC2_APPS_CLK 103
#define GCC_SDCC2_AHB_CLK 104
#define GCC_SDCC3_APPS_CLK 105
#define GCC_SDCC3_AHB_CLK 106
#define GCC_SDCC4_APPS_CLK 107
#define GCC_SDCC4_AHB_CLK 108
#define GCC_BLSP1_AHB_CLK 109
#define GCC_BLSP1_SLEEP_CLK 110
#define GCC_BLSP1_QUP1_SPI_APPS_CLK 111
#define GCC_BLSP1_QUP1_I2C_APPS_CLK 112
#define GCC_BLSP1_UART1_APPS_CLK 113
#define GCC_BLSP1_QUP2_SPI_APPS_CLK 114
#define GCC_BLSP1_QUP2_I2C_APPS_CLK 115
#define GCC_BLSP1_UART2_APPS_CLK 116
#define GCC_BLSP1_QUP3_SPI_APPS_CLK 117
#define GCC_BLSP1_QUP3_I2C_APPS_CLK 118
#define GCC_BLSP1_UART3_APPS_CLK 119
#define GCC_BLSP1_QUP4_SPI_APPS_CLK 120
#define GCC_BLSP1_QUP4_I2C_APPS_CLK 121
#define GCC_BLSP1_UART4_APPS_CLK 122
#define GCC_BLSP1_QUP5_SPI_APPS_CLK 123
#define GCC_BLSP1_QUP5_I2C_APPS_CLK 124
#define GCC_BLSP1_UART5_APPS_CLK 125
#define GCC_BLSP1_QUP6_SPI_APPS_CLK 126
#define GCC_BLSP1_QUP6_I2C_APPS_CLK 127
#define GCC_BLSP1_UART6_APPS_CLK 128
#define GCC_BLSP2_AHB_CLK 129
#define GCC_BLSP2_SLEEP_CLK 130
#define GCC_BLSP2_QUP1_SPI_APPS_CLK 131
#define GCC_BLSP2_QUP1_I2C_APPS_CLK 132
#define GCC_BLSP2_UART1_APPS_CLK 133
#define GCC_BLSP2_QUP2_SPI_APPS_CLK 134
#define GCC_BLSP2_QUP2_I2C_APPS_CLK 135
#define GCC_BLSP2_UART2_APPS_CLK 136
#define GCC_BLSP2_QUP3_SPI_APPS_CLK 137
#define GCC_BLSP2_QUP3_I2C_APPS_CLK 138
#define GCC_BLSP2_UART3_APPS_CLK 139
#define GCC_BLSP2_QUP4_SPI_APPS_CLK 140
#define GCC_BLSP2_QUP4_I2C_APPS_CLK 141
#define GCC_BLSP2_UART4_APPS_CLK 142
#define GCC_BLSP2_QUP5_SPI_APPS_CLK 143
#define GCC_BLSP2_QUP5_I2C_APPS_CLK 144
#define GCC_BLSP2_UART5_APPS_CLK 145
#define GCC_BLSP2_QUP6_SPI_APPS_CLK 146
#define GCC_BLSP2_QUP6_I2C_APPS_CLK 147
#define GCC_BLSP2_UART6_APPS_CLK 148
#define GCC_PDM_AHB_CLK 149
#define GCC_PDM_XO4_CLK 150
#define GCC_PDM2_CLK 151
#define GCC_PRNG_AHB_CLK 152
#define GCC_TSIF_AHB_CLK 153
#define GCC_TSIF_REF_CLK 154
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 155
#define GCC_TCSR_AHB_CLK 156
#define GCC_BOOT_ROM_AHB_CLK 157
#define GCC_MSG_RAM_AHB_CLK 158
#define GCC_TLMM_AHB_CLK 159
#define GCC_TLMM_CLK 160
#define GCC_MPM_AHB_CLK 161
#define GCC_SPMI_SER_CLK 162
#define GCC_SPMI_CNOC_AHB_CLK 163
#define GCC_CE1_CLK 164
#define GCC_CE1_AXI_CLK 165
#define GCC_CE1_AHB_CLK 166
#define GCC_BIMC_HMSS_AXI_CLK 167
#define GCC_BIMC_GFX_CLK 168
#define GCC_HMSS_AHB_CLK 169
#define GCC_HMSS_SLV_AXI_CLK 170
#define GCC_HMSS_MSTR_AXI_CLK 171
#define GCC_HMSS_RBCPR_CLK 172
#define GCC_GP1_CLK 173
#define GCC_GP2_CLK 174
#define GCC_GP3_CLK 175
#define GCC_PCIE_0_SLV_AXI_CLK 176
#define GCC_PCIE_0_MSTR_AXI_CLK 177
#define GCC_PCIE_0_CFG_AHB_CLK 178
#define GCC_PCIE_0_AUX_CLK 179
#define GCC_PCIE_0_PIPE_CLK 180
#define GCC_PCIE_1_SLV_AXI_CLK 181
#define GCC_PCIE_1_MSTR_AXI_CLK 182
#define GCC_PCIE_1_CFG_AHB_CLK 183
#define GCC_PCIE_1_AUX_CLK 184
#define GCC_PCIE_1_PIPE_CLK 185
#define GCC_PCIE_2_SLV_AXI_CLK 186
#define GCC_PCIE_2_MSTR_AXI_CLK 187
#define GCC_PCIE_2_CFG_AHB_CLK 188
#define GCC_PCIE_2_AUX_CLK 189
#define GCC_PCIE_2_PIPE_CLK 190
#define GCC_PCIE_PHY_CFG_AHB_CLK 191
#define GCC_PCIE_PHY_AUX_CLK 192
#define GCC_UFS_AXI_CLK 193
#define GCC_UFS_AHB_CLK 194
#define GCC_UFS_TX_CFG_CLK 195
#define GCC_UFS_RX_CFG_CLK 196
#define GCC_UFS_TX_SYMBOL_0_CLK 197
#define GCC_UFS_RX_SYMBOL_0_CLK 198
#define GCC_UFS_RX_SYMBOL_1_CLK 199
#define GCC_UFS_UNIPRO_CORE_CLK 200
#define GCC_UFS_ICE_CORE_CLK 201
#define GCC_UFS_SYS_CLK_CORE_CLK 202
#define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203
#define GCC_AGGRE0_SNOC_AXI_CLK 204
#define GCC_AGGRE0_CNOC_AHB_CLK 205
#define GCC_SMMU_AGGRE0_AXI_CLK 206
#define GCC_SMMU_AGGRE0_AHB_CLK 207
#define GCC_AGGRE1_PNOC_AHB_CLK 208
#define GCC_AGGRE2_UFS_AXI_CLK 209
#define GCC_AGGRE2_USB3_AXI_CLK 210
#define GCC_QSPI_AHB_CLK 211
#define GCC_QSPI_SER_CLK 212
#define GCC_USB3_CLKREF_CLK 213
#define GCC_HDMI_CLKREF_CLK 214
#define GCC_UFS_CLKREF_CLK 215
#define GCC_PCIE_CLKREF_CLK 216
#define GCC_RX2_USB2_CLKREF_CLK 217
#define GCC_RX1_USB2_CLKREF_CLK 218
#define GCC_SYSTEM_NOC_BCR 0
#define GCC_CONFIG_NOC_BCR 1
#define GCC_PERIPH_NOC_BCR 2
#define GCC_IMEM_BCR 3
#define GCC_MMSS_BCR 4
#define GCC_PIMEM_BCR 5
#define GCC_QDSS_BCR 6
#define GCC_USB_30_BCR 7
#define GCC_USB_20_BCR 8
#define GCC_QUSB2PHY_PRIM_BCR 9
#define GCC_QUSB2PHY_SEC_BCR 10
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 11
#define GCC_SDCC1_BCR 12
#define GCC_SDCC2_BCR 13
#define GCC_SDCC3_BCR 14
#define GCC_SDCC4_BCR 15
#define GCC_BLSP1_BCR 16
#define GCC_BLSP1_QUP1_BCR 17
#define GCC_BLSP1_UART1_BCR 18
#define GCC_BLSP1_QUP2_BCR 19
#define GCC_BLSP1_UART2_BCR 20
#define GCC_BLSP1_QUP3_BCR 21
#define GCC_BLSP1_UART3_BCR 22
#define GCC_BLSP1_QUP4_BCR 23
#define GCC_BLSP1_UART4_BCR 24
#define GCC_BLSP1_QUP5_BCR 25
#define GCC_BLSP1_UART5_BCR 26
#define GCC_BLSP1_QUP6_BCR 27
#define GCC_BLSP1_UART6_BCR 28
#define GCC_BLSP2_BCR 29
#define GCC_BLSP2_QUP1_BCR 30
#define GCC_BLSP2_UART1_BCR 31
#define GCC_BLSP2_QUP2_BCR 32
#define GCC_BLSP2_UART2_BCR 33
#define GCC_BLSP2_QUP3_BCR 34
#define GCC_BLSP2_UART3_BCR 35
#define GCC_BLSP2_QUP4_BCR 36
#define GCC_BLSP2_UART4_BCR 37
#define GCC_BLSP2_QUP5_BCR 38
#define GCC_BLSP2_UART5_BCR 39
#define GCC_BLSP2_QUP6_BCR 40
#define GCC_BLSP2_UART6_BCR 41
#define GCC_PDM_BCR 42
#define GCC_PRNG_BCR 43
#define GCC_TSIF_BCR 44
#define GCC_TCSR_BCR 45
#define GCC_BOOT_ROM_BCR 46
#define GCC_MSG_RAM_BCR 47
#define GCC_TLMM_BCR 48
#define GCC_MPM_BCR 49
#define GCC_SEC_CTRL_BCR 50
#define GCC_SPMI_BCR 51
#define GCC_SPDM_BCR 52
#define GCC_CE1_BCR 53
#define GCC_BIMC_BCR 54
#define GCC_SNOC_BUS_TIMEOUT0_BCR 55
#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
#define GCC_SNOC_BUS_TIMEOUT1_BCR 57
#define GCC_SNOC_BUS_TIMEOUT3_BCR 58
#define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59
#define GCC_PNOC_BUS_TIMEOUT0_BCR 60
#define GCC_PNOC_BUS_TIMEOUT1_BCR 61
#define GCC_PNOC_BUS_TIMEOUT2_BCR 62
#define GCC_PNOC_BUS_TIMEOUT3_BCR 63
#define GCC_PNOC_BUS_TIMEOUT4_BCR 64
#define GCC_CNOC_BUS_TIMEOUT0_BCR 65
#define GCC_CNOC_BUS_TIMEOUT1_BCR 66
#define GCC_CNOC_BUS_TIMEOUT2_BCR 67
#define GCC_CNOC_BUS_TIMEOUT3_BCR 68
#define GCC_CNOC_BUS_TIMEOUT4_BCR 69
#define GCC_CNOC_BUS_TIMEOUT5_BCR 70
#define GCC_CNOC_BUS_TIMEOUT6_BCR 71
#define GCC_CNOC_BUS_TIMEOUT7_BCR 72
#define GCC_CNOC_BUS_TIMEOUT8_BCR 73
#define GCC_CNOC_BUS_TIMEOUT9_BCR 74
#define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75
#define GCC_APB2JTAG_BCR 76
#define GCC_RBCPR_CX_BCR 77
#define GCC_RBCPR_MX_BCR 78
#define GCC_PCIE_0_BCR 79
#define GCC_PCIE_0_PHY_BCR 80
#define GCC_PCIE_1_BCR 81
#define GCC_PCIE_1_PHY_BCR 82
#define GCC_PCIE_2_BCR 83
#define GCC_PCIE_2_PHY_BCR 84
#define GCC_PCIE_PHY_BCR 85
#define GCC_DCD_BCR 86
#define GCC_OBT_ODT_BCR 87
#define GCC_UFS_BCR 88
#define GCC_SSC_BCR 89
#define GCC_VS_BCR 90
#define GCC_AGGRE0_NOC_BCR 91
#define GCC_AGGRE1_NOC_BCR 92
#define GCC_AGGRE2_NOC_BCR 93
#define GCC_DCC_BCR 94
#define GCC_IPA_BCR 95
#define GCC_QSPI_BCR 96
#define GCC_SKL_BCR 97
#define GCC_MSMPU_BCR 98
#define GCC_MSS_Q6_BCR 99
#define GCC_QREFS_VBG_CAL_BCR 100
#endif

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/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _DT_BINDINGS_CLK_MSM_MMCC_8996_H
#define _DT_BINDINGS_CLK_MSM_MMCC_8996_H
#define MMPLL0_EARLY 0
#define MMPLL0_PLL 1
#define MMPLL1_EARLY 2
#define MMPLL1_PLL 3
#define MMPLL2_EARLY 4
#define MMPLL2_PLL 5
#define MMPLL3_EARLY 6
#define MMPLL3_PLL 7
#define MMPLL4_EARLY 8
#define MMPLL4_PLL 9
#define MMPLL5_EARLY 10
#define MMPLL5_PLL 11
#define MMPLL8_EARLY 12
#define MMPLL8_PLL 13
#define MMPLL9_EARLY 14
#define MMPLL9_PLL 15
#define AHB_CLK_SRC 16
#define AXI_CLK_SRC 17
#define MAXI_CLK_SRC 18
#define DSA_CORE_CLK_SRC 19
#define GFX3D_CLK_SRC 20
#define RBBMTIMER_CLK_SRC 21
#define ISENSE_CLK_SRC 22
#define RBCPR_CLK_SRC 23
#define VIDEO_CORE_CLK_SRC 24
#define VIDEO_SUBCORE0_CLK_SRC 25
#define VIDEO_SUBCORE1_CLK_SRC 26
#define PCLK0_CLK_SRC 27
#define PCLK1_CLK_SRC 28
#define MDP_CLK_SRC 29
#define EXTPCLK_CLK_SRC 30
#define VSYNC_CLK_SRC 31
#define HDMI_CLK_SRC 32
#define BYTE0_CLK_SRC 33
#define BYTE1_CLK_SRC 34
#define ESC0_CLK_SRC 35
#define ESC1_CLK_SRC 36
#define CAMSS_GP0_CLK_SRC 37
#define CAMSS_GP1_CLK_SRC 38
#define MCLK0_CLK_SRC 39
#define MCLK1_CLK_SRC 40
#define MCLK2_CLK_SRC 41
#define MCLK3_CLK_SRC 42
#define CCI_CLK_SRC 43
#define CSI0PHYTIMER_CLK_SRC 44
#define CSI1PHYTIMER_CLK_SRC 45
#define CSI2PHYTIMER_CLK_SRC 46
#define CSIPHY0_3P_CLK_SRC 47
#define CSIPHY1_3P_CLK_SRC 48
#define CSIPHY2_3P_CLK_SRC 49
#define JPEG0_CLK_SRC 50
#define JPEG2_CLK_SRC 51
#define JPEG_DMA_CLK_SRC 52
#define VFE0_CLK_SRC 53
#define VFE1_CLK_SRC 54
#define CPP_CLK_SRC 55
#define CSI0_CLK_SRC 56
#define CSI1_CLK_SRC 57
#define CSI2_CLK_SRC 58
#define CSI3_CLK_SRC 59
#define FD_CORE_CLK_SRC 60
#define MMSS_CXO_CLK 61
#define MMSS_SLEEPCLK_CLK 62
#define MMSS_MMAGIC_AHB_CLK 63
#define MMSS_MMAGIC_CFG_AHB_CLK 64
#define MMSS_MISC_AHB_CLK 65
#define MMSS_MISC_CXO_CLK 66
#define MMSS_BTO_AHB_CLK 67
#define MMSS_MMAGIC_AXI_CLK 68
#define MMSS_S0_AXI_CLK 69
#define MMSS_MMAGIC_MAXI_CLK 70
#define DSA_CORE_CLK 71
#define DSA_NOC_CFG_AHB_CLK 72
#define MMAGIC_CAMSS_AXI_CLK 73
#define MMAGIC_CAMSS_NOC_CFG_AHB_CLK 74
#define THROTTLE_CAMSS_CXO_CLK 75
#define THROTTLE_CAMSS_AHB_CLK 76
#define THROTTLE_CAMSS_AXI_CLK 77
#define SMMU_VFE_AHB_CLK 78
#define SMMU_VFE_AXI_CLK 79
#define SMMU_CPP_AHB_CLK 80
#define SMMU_CPP_AXI_CLK 81
#define SMMU_JPEG_AHB_CLK 82
#define SMMU_JPEG_AXI_CLK 83
#define MMAGIC_MDSS_AXI_CLK 84
#define MMAGIC_MDSS_NOC_CFG_AHB_CLK 85
#define THROTTLE_MDSS_CXO_CLK 86
#define THROTTLE_MDSS_AHB_CLK 87
#define THROTTLE_MDSS_AXI_CLK 88
#define SMMU_ROT_AHB_CLK 89
#define SMMU_ROT_AXI_CLK 90
#define SMMU_MDP_AHB_CLK 91
#define SMMU_MDP_AXI_CLK 92
#define MMAGIC_VIDEO_AXI_CLK 93
#define MMAGIC_VIDEO_NOC_CFG_AHB_CLK 94
#define THROTTLE_VIDEO_CXO_CLK 95
#define THROTTLE_VIDEO_AHB_CLK 96
#define THROTTLE_VIDEO_AXI_CLK 97
#define SMMU_VIDEO_AHB_CLK 98
#define SMMU_VIDEO_AXI_CLK 99
#define MMAGIC_BIMC_AXI_CLK 100
#define MMAGIC_BIMC_NOC_CFG_AHB_CLK 101
#define GPU_GX_GFX3D_CLK 102
#define GPU_GX_RBBMTIMER_CLK 103
#define GPU_AHB_CLK 104
#define GPU_AON_ISENSE_CLK 105
#define VMEM_MAXI_CLK 106
#define VMEM_AHB_CLK 107
#define MMSS_RBCPR_CLK 108
#define MMSS_RBCPR_AHB_CLK 109
#define VIDEO_CORE_CLK 110
#define VIDEO_AXI_CLK 111
#define VIDEO_MAXI_CLK 112
#define VIDEO_AHB_CLK 113
#define VIDEO_SUBCORE0_CLK 114
#define VIDEO_SUBCORE1_CLK 115
#define MDSS_AHB_CLK 116
#define MDSS_HDMI_AHB_CLK 117
#define MDSS_AXI_CLK 118
#define MDSS_PCLK0_CLK 119
#define MDSS_PCLK1_CLK 120
#define MDSS_MDP_CLK 121
#define MDSS_EXTPCLK_CLK 122
#define MDSS_VSYNC_CLK 123
#define MDSS_HDMI_CLK 124
#define MDSS_BYTE0_CLK 125
#define MDSS_BYTE1_CLK 126
#define MDSS_ESC0_CLK 127
#define MDSS_ESC1_CLK 128
#define CAMSS_TOP_AHB_CLK 129
#define CAMSS_AHB_CLK 130
#define CAMSS_MICRO_AHB_CLK 131
#define CAMSS_GP0_CLK 132
#define CAMSS_GP1_CLK 133
#define CAMSS_MCLK0_CLK 134
#define CAMSS_MCLK1_CLK 135
#define CAMSS_MCLK2_CLK 136
#define CAMSS_MCLK3_CLK 137
#define CAMSS_CCI_CLK 138
#define CAMSS_CCI_AHB_CLK 139
#define CAMSS_CSI0PHYTIMER_CLK 140
#define CAMSS_CSI1PHYTIMER_CLK 141
#define CAMSS_CSI2PHYTIMER_CLK 142
#define CAMSS_CSIPHY0_3P_CLK 143
#define CAMSS_CSIPHY1_3P_CLK 144
#define CAMSS_CSIPHY2_3P_CLK 145
#define CAMSS_JPEG0_CLK 146
#define CAMSS_JPEG2_CLK 147
#define CAMSS_JPEG_DMA_CLK 148
#define CAMSS_JPEG_AHB_CLK 149
#define CAMSS_JPEG_AXI_CLK 150
#define CAMSS_VFE_AHB_CLK 151
#define CAMSS_VFE_AXI_CLK 152
#define CAMSS_VFE0_CLK 153
#define CAMSS_VFE0_STREAM_CLK 154
#define CAMSS_VFE0_AHB_CLK 155
#define CAMSS_VFE1_CLK 156
#define CAMSS_VFE1_STREAM_CLK 157
#define CAMSS_VFE1_AHB_CLK 158
#define CAMSS_CSI_VFE0_CLK 159
#define CAMSS_CSI_VFE1_CLK 160
#define CAMSS_CPP_VBIF_AHB_CLK 161
#define CAMSS_CPP_AXI_CLK 162
#define CAMSS_CPP_CLK 163
#define CAMSS_CPP_AHB_CLK 164
#define CAMSS_CSI0_CLK 165
#define CAMSS_CSI0_AHB_CLK 166
#define CAMSS_CSI0PHY_CLK 167
#define CAMSS_CSI0RDI_CLK 168
#define CAMSS_CSI0PIX_CLK 169
#define CAMSS_CSI1_CLK 170
#define CAMSS_CSI1_AHB_CLK 171
#define CAMSS_CSI1PHY_CLK 172
#define CAMSS_CSI1RDI_CLK 173
#define CAMSS_CSI1PIX_CLK 174
#define CAMSS_CSI2_CLK 175
#define CAMSS_CSI2_AHB_CLK 176
#define CAMSS_CSI2PHY_CLK 177
#define CAMSS_CSI2RDI_CLK 178
#define CAMSS_CSI2PIX_CLK 179
#define CAMSS_CSI3_CLK 180
#define CAMSS_CSI3_AHB_CLK 181
#define CAMSS_CSI3PHY_CLK 182
#define CAMSS_CSI3RDI_CLK 183
#define CAMSS_CSI3PIX_CLK 184
#define CAMSS_ISPIF_AHB_CLK 185
#define FD_CORE_CLK 186
#define FD_CORE_UAR_CLK 187
#define FD_AHB_CLK 188
#define MMSS_SPDM_CSI0_CLK 189
#define MMSS_SPDM_JPEG_DMA_CLK 190
#define MMSS_SPDM_CPP_CLK 191
#define MMSS_SPDM_PCLK0_CLK 192
#define MMSS_SPDM_AHB_CLK 193
#define MMSS_SPDM_GFX3D_CLK 194
#define MMSS_SPDM_PCLK1_CLK 195
#define MMSS_SPDM_JPEG2_CLK 196
#define MMSS_SPDM_DEBUG_CLK 197
#define MMSS_SPDM_VFE1_CLK 198
#define MMSS_SPDM_VFE0_CLK 199
#define MMSS_SPDM_VIDEO_CORE_CLK 200
#define MMSS_SPDM_AXI_CLK 201
#define MMSS_SPDM_MDP_CLK 202
#define MMSS_SPDM_JPEG0_CLK 203
#define MMSS_SPDM_RM_AXI_CLK 204
#define MMSS_SPDM_RM_MAXI_CLK 205
#define MMAGICAHB_BCR 0
#define MMAGIC_CFG_BCR 1
#define MISC_BCR 2
#define BTO_BCR 3
#define MMAGICAXI_BCR 4
#define MMAGICMAXI_BCR 5
#define DSA_BCR 6
#define MMAGIC_CAMSS_BCR 7
#define THROTTLE_CAMSS_BCR 8
#define SMMU_VFE_BCR 9
#define SMMU_CPP_BCR 10
#define SMMU_JPEG_BCR 11
#define MMAGIC_MDSS_BCR 12
#define THROTTLE_MDSS_BCR 13
#define SMMU_ROT_BCR 14
#define SMMU_MDP_BCR 15
#define MMAGIC_VIDEO_BCR 16
#define THROTTLE_VIDEO_BCR 17
#define SMMU_VIDEO_BCR 18
#define MMAGIC_BIMC_BCR 19
#define GPU_GX_BCR 20
#define GPU_BCR 21
#define GPU_AON_BCR 22
#define VMEM_BCR 23
#define MMSS_RBCPR_BCR 24
#define VIDEO_BCR 25
#define MDSS_BCR 26
#define CAMSS_TOP_BCR 27
#define CAMSS_AHB_BCR 28
#define CAMSS_MICRO_BCR 29
#define CAMSS_CCI_BCR 30
#define CAMSS_PHY0_BCR 31
#define CAMSS_PHY1_BCR 32
#define CAMSS_PHY2_BCR 33
#define CAMSS_CSIPHY0_3P_BCR 34
#define CAMSS_CSIPHY1_3P_BCR 35
#define CAMSS_CSIPHY2_3P_BCR 36
#define CAMSS_JPEG_BCR 37
#define CAMSS_VFE_BCR 38
#define CAMSS_VFE0_BCR 39
#define CAMSS_VFE1_BCR 40
#define CAMSS_CSI_VFE0_BCR 41
#define CAMSS_CSI_VFE1_BCR 42
#define CAMSS_CPP_TOP_BCR 43
#define CAMSS_CPP_BCR 44
#define CAMSS_CSI0_BCR 45
#define CAMSS_CSI0RDI_BCR 46
#define CAMSS_CSI0PIX_BCR 47
#define CAMSS_CSI1_BCR 48
#define CAMSS_CSI1RDI_BCR 49
#define CAMSS_CSI1PIX_BCR 50
#define CAMSS_CSI2_BCR 51
#define CAMSS_CSI2RDI_BCR 52
#define CAMSS_CSI2PIX_BCR 53
#define CAMSS_CSI3_BCR 54
#define CAMSS_CSI3RDI_BCR 55
#define CAMSS_CSI3PIX_BCR 56
#define CAMSS_ISPIF_BCR 57
#define FD_BCR 58
#define MMSS_SPDM_RM_BCR 59
#endif