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staging: slicoss: remove the staging driver
A "real" driver for this hardware has now landed in the networking tree, so remove this old staging driver so that we don't have multiple drivers for the same hardware, and so people don't waste their time trying to clean up this old code. Cc: Lior Dotan <liodot@gmail.com> Cc: Christopher Harrer <charrer@alacritech.com> Cc: David Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Greg Kroah-Hartman
parent
4ec941d68c
commit
0af72df267
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@ -11566,12 +11566,6 @@ L: linux-fbdev@vger.kernel.org
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S: Maintained
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F: drivers/staging/sm750fb/
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STAGING - SLICOSS
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M: Lior Dotan <liodot@gmail.com>
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M: Christopher Harrer <charrer@alacritech.com>
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S: Odd Fixes
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F: drivers/staging/slicoss/
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STAGING - SPEAKUP CONSOLE SPEECH DRIVER
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M: William Hubbs <w.d.hubbs@gmail.com>
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M: Chris Brannon <chris@the-brannons.com>
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@ -24,8 +24,6 @@ menuconfig STAGING
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if STAGING
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source "drivers/staging/slicoss/Kconfig"
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source "drivers/staging/wlan-ng/Kconfig"
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source "drivers/staging/comedi/Kconfig"
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@ -1,7 +1,6 @@
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# Makefile for staging directory
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obj-y += media/
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obj-$(CONFIG_SLICOSS) += slicoss/
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obj-$(CONFIG_PRISM2_USB) += wlan-ng/
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obj-$(CONFIG_COMEDI) += comedi/
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obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
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@ -1,14 +0,0 @@
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config SLICOSS
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tristate "Alacritech Gigabit IS-NIC support"
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depends on PCI && X86 && NET
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default n
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help
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This driver supports Alacritech's IS-NIC gigabit ethernet cards.
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This includes the following devices:
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Mojave cards (single port PCI Gigabit) both copper and fiber
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Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
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Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
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To compile this driver as a module, choose M here: the module
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will be called slicoss.
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@ -1 +0,0 @@
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obj-$(CONFIG_SLICOSS) += slicoss.o
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@ -1,7 +0,0 @@
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This driver is supposed to support:
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Mojave cards (single port PCI Gigabit) both copper and fiber
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Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
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Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
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The driver was actually tested on Oasis and Kalahari cards.
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@ -1,36 +0,0 @@
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TODO:
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- move firmware loading to request_firmware()
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- remove direct memory access of structures
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- any remaining sparse and checkpatch.pl warnings
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- use net_device_ops
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- use dev->stats rather than adapter->stats
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- don't cast netdev_priv it is already void
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- GET RID OF MACROS
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- work on all architectures
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- without CONFIG_X86_64 confusion
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- do 64 bit correctly
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- don't depend on order of union
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- get rid of ASSERT(), use BUG() instead but only where necessary
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looks like most aren't really useful
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- no new SIOCDEVPRIVATE ioctl allowed
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- don't use module_param for configuring interrupt mitigation
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use ethtool instead
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- reorder code to elminate use of forward declarations
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- don't keep private linked list of drivers.
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- use PCI_DEVICE()
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- do ethtool correctly using ethtool_ops
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- NAPI?
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- wasted overhead of extra stats
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- state variables for things that are
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easily available and shouldn't be kept in card structure, cardnum, ...
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slotnumber, events, ...
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- volatile == bad design => bad code
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- locking too fine grained, not designed just throw more locks
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at problem
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Please send patches to:
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Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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and Cc: Lior Dotan <liodot@gmail.com> and Christopher Harrer
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<charrer@alacritech.com> as well as they are also able to test out any
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changes.
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@ -1,568 +0,0 @@
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/**************************************************************************
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*
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* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* The views and conclusions contained in the software and documentation
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* are those of the authors and should not be interpreted as representing
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* official policies, either expressed or implied, of Alacritech, Inc.
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*
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**************************************************************************/
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/*
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* FILENAME: slic.h
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*
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* This is the base set of header definitions for the SLICOSS driver.
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*/
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#ifndef __SLIC_DRIVER_H__
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#define __SLIC_DRIVER_H__
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/* firmware stuff */
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#define OASIS_UCODE_VERS_STRING "1.2"
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#define OASIS_UCODE_VERS_DATE "2006/03/27 15:10:37"
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#define OASIS_UCODE_HOSTIF_ID 3
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#define MOJAVE_UCODE_VERS_STRING "1.2"
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#define MOJAVE_UCODE_VERS_DATE "2006/03/27 15:12:22"
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#define MOJAVE_UCODE_HOSTIF_ID 3
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#define GB_RCVUCODE_VERS_STRING "1.2"
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#define GB_RCVUCODE_VERS_DATE "2006/03/27 15:12:15"
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static u32 oasis_rcv_ucode_len = 512;
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static u32 gb_rcv_ucode_len = 512;
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#define SECTION_SIZE 65536
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#define SLIC_RSPQ_PAGES_GB 10
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#define SLIC_RSPQ_BUFSINPAGE (PAGE_SIZE / SLIC_RSPBUF_SIZE)
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struct slic_rspqueue {
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u32 offset;
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u32 pageindex;
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u32 num_pages;
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struct slic_rspbuf *rspbuf;
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u32 *vaddr[SLIC_RSPQ_PAGES_GB];
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dma_addr_t paddr[SLIC_RSPQ_PAGES_GB];
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};
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#define SLIC_RCVQ_EXPANSION 1
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#define SLIC_RCVQ_ENTRIES (256 * SLIC_RCVQ_EXPANSION)
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#define SLIC_RCVQ_MINENTRIES (SLIC_RCVQ_ENTRIES / 2)
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#define SLIC_RCVQ_MAX_PROCESS_ISR ((SLIC_RCVQ_ENTRIES * 4))
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#define SLIC_RCVQ_RCVBUFSIZE 2048
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#define SLIC_RCVQ_FILLENTRIES (16 * SLIC_RCVQ_EXPANSION)
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#define SLIC_RCVQ_FILLTHRESH (SLIC_RCVQ_ENTRIES - SLIC_RCVQ_FILLENTRIES)
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struct slic_rcvqueue {
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struct sk_buff *head;
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struct sk_buff *tail;
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u32 count;
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u32 size;
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u32 errors;
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};
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struct slic_rcvbuf_info {
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u32 id;
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u32 starttime;
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u32 stoptime;
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u32 slicworld;
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u32 lasttime;
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u32 lastid;
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};
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/*
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* SLIC Handle structure. Used to restrict handle values to
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* 32 bits by using an index rather than an address.
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* Simplifies ucode in 64-bit systems
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*/
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struct slic_handle_word {
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union {
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struct {
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ushort index;
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ushort bottombits; /* to denote num bufs to card */
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} parts;
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u32 whole;
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} handle;
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};
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struct slic_handle {
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struct slic_handle_word token; /* token passed between host and card*/
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ushort type;
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void *address; /* actual address of the object*/
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ushort offset;
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struct slic_handle *other_handle;
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struct slic_handle *next;
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};
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#define SLIC_HANDLE_FREE 0x0000
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#define SLIC_HANDLE_DATA 0x0001
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#define SLIC_HANDLE_CMD 0x0002
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#define SLIC_HANDLE_CONTEXT 0x0003
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#define SLIC_HANDLE_TEAM 0x0004
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#define handle_index handle.parts.index
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#define handle_bottom handle.parts.bottombits
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#define handle_token handle.whole
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#define SLIC_HOSTCMD_SIZE 512
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struct slic_hostcmd {
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struct slic_host64_cmd cmd64;
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u32 type;
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struct sk_buff *skb;
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u32 paddrl;
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u32 paddrh;
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u32 busy;
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u32 cmdsize;
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ushort numbufs;
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struct slic_handle *pslic_handle;/* handle associated with command */
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struct slic_hostcmd *next;
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struct slic_hostcmd *next_all;
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};
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#define SLIC_CMDQ_CMDSINPAGE (PAGE_SIZE / SLIC_HOSTCMD_SIZE)
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#define SLIC_CMD_DUMB 3
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#define SLIC_CMDQ_INITCMDS 256
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#define SLIC_CMDQ_MAXCMDS 256
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#define SLIC_CMDQ_MAXOUTSTAND SLIC_CMDQ_MAXCMDS
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#define SLIC_CMDQ_MAXPAGES (SLIC_CMDQ_MAXCMDS / SLIC_CMDQ_CMDSINPAGE)
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#define SLIC_CMDQ_INITPAGES (SLIC_CMDQ_INITCMDS / SLIC_CMDQ_CMDSINPAGE)
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struct slic_cmdqmem {
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int pagecnt;
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u32 *pages[SLIC_CMDQ_MAXPAGES];
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dma_addr_t dma_pages[SLIC_CMDQ_MAXPAGES];
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};
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struct slic_cmdqueue {
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struct slic_hostcmd *head;
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struct slic_hostcmd *tail;
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int count;
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spinlock_t lock;
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};
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#define SLIC_MAX_CARDS 32
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#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
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struct mcast_address {
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unsigned char address[6];
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struct mcast_address *next;
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};
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#define CARD_DOWN 0x00000000
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#define CARD_UP 0x00000001
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#define CARD_FAIL 0x00000002
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#define CARD_DIAG 0x00000003
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#define CARD_SLEEP 0x00000004
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#define ADAPT_DOWN 0x00
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#define ADAPT_UP 0x01
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#define ADAPT_FAIL 0x02
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#define ADAPT_RESET 0x03
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#define ADAPT_SLEEP 0x04
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#define ADAPT_FLAGS_BOOTTIME 0x0001
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#define ADAPT_FLAGS_IS64BIT 0x0002
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#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
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#define ADAPT_FLAGS_FIBERMEDIA 0x0008
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#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
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#define ADAPT_FLAGS_INT_REGISTERED 0x0020
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#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
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#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
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#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
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#define LINK_DOWN 0x00
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#define LINK_CONFIG 0x01
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#define LINK_UP 0x02
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#define LINK_10MB 0x00
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#define LINK_100MB 0x01
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#define LINK_AUTOSPEED 0x02
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#define LINK_1000MB 0x03
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#define LINK_10000MB 0x04
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#define LINK_HALFD 0x00
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#define LINK_FULLD 0x01
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#define LINK_AUTOD 0x02
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#define MAC_DIRECTED 0x00000001
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#define MAC_BCAST 0x00000002
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#define MAC_MCAST 0x00000004
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#define MAC_PROMISC 0x00000008
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#define MAC_LOOPBACK 0x00000010
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#define MAC_ALLMCAST 0x00000020
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static inline const char *slic_linkstate(unsigned char x)
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{
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return ((x == LINK_DOWN) ? "Down" : "Up ");
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}
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static inline const char *slic_adapter_state(unsigned char x)
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{
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return ((x == ADAPT_UP) ? "UP" : "Down");
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}
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static inline const char *slic_card_state(uint x)
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{
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return ((x == CARD_UP) ? "UP" : "Down");
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}
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struct slic_iface_stats {
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/*
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* Stats
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*/
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u64 xmt_bytes;
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u64 xmt_ucast;
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u64 xmt_mcast;
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u64 xmt_bcast;
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u64 xmt_errors;
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u64 xmt_discards;
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u64 xmit_collisions;
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u64 xmit_excess_xmit_collisions;
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u64 rcv_bytes;
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u64 rcv_ucast;
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u64 rcv_mcast;
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u64 rcv_bcast;
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u64 rcv_errors;
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u64 rcv_discards;
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};
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struct sliccp_stats {
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u64 xmit_tcp_segs;
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u64 xmit_tcp_bytes;
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u64 rcv_tcp_segs;
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u64 rcv_tcp_bytes;
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};
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struct slicnet_stats {
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struct sliccp_stats tcp;
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struct slic_iface_stats iface;
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};
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#define SLIC_LOADTIMER_PERIOD 1
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#define SLIC_INTAGG_DEFAULT 200
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#define SLIC_LOAD_0 0
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#define SLIC_INTAGG_0 0
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#define SLIC_LOAD_1 8000
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#define SLIC_LOAD_2 10000
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#define SLIC_LOAD_3 12000
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#define SLIC_LOAD_4 14000
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#define SLIC_LOAD_5 16000
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#define SLIC_INTAGG_1 50
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#define SLIC_INTAGG_2 100
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#define SLIC_INTAGG_3 150
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#define SLIC_INTAGG_4 200
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#define SLIC_INTAGG_5 250
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#define SLIC_LOAD_1GB 3000
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#define SLIC_LOAD_2GB 6000
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#define SLIC_LOAD_3GB 12000
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#define SLIC_LOAD_4GB 24000
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#define SLIC_LOAD_5GB 48000
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#define SLIC_INTAGG_1GB 50
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#define SLIC_INTAGG_2GB 75
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#define SLIC_INTAGG_3GB 100
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#define SLIC_INTAGG_4GB 100
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#define SLIC_INTAGG_5GB 100
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struct ether_header {
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unsigned char ether_dhost[6];
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unsigned char ether_shost[6];
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ushort ether_type;
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};
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struct sliccard {
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uint busnumber;
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uint slotnumber;
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uint state;
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uint cardnum;
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uint card_size;
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uint adapters_activated;
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uint adapters_allocated;
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uint adapters_sleeping;
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uint gennumber;
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u32 events;
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u32 loadlevel_current;
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u32 load;
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uint reset_in_progress;
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u32 pingstatus;
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u32 bad_pingstatus;
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struct timer_list loadtimer;
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u32 loadtimerset;
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uint config_set;
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struct slic_config config;
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struct adapter *master;
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struct adapter *adapter[SLIC_MAX_PORTS];
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struct sliccard *next;
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u32 error_interrupts;
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u32 error_rmiss_interrupts;
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u32 rcv_interrupts;
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u32 xmit_interrupts;
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u32 num_isrs;
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u32 false_interrupts;
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u32 max_isr_rcvs;
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u32 max_isr_xmits;
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u32 rcv_interrupt_yields;
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u32 tx_packets;
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u32 debug_ix;
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ushort reg_type[32];
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ushort reg_offset[32];
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u32 reg_value[32];
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u32 reg_valueh[32];
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};
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#define NUM_CFG_SPACES 2
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#define NUM_CFG_REGS 64
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#define NUM_CFG_REG_ULONGS (NUM_CFG_REGS / sizeof(u32))
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struct physcard {
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struct adapter *adapter[SLIC_MAX_PORTS];
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struct physcard *next;
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uint adapters_allocd;
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/*
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* the following is not currently needed
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* u32 bridge_busnum;
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* u32 bridge_cfg[NUM_CFG_SPACES][NUM_CFG_REG_ULONGS];
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*/
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};
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struct base_driver {
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spinlock_t driver_lock;
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u32 num_slic_cards;
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u32 num_slic_ports;
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u32 num_slic_ports_active;
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u32 dynamic_intagg;
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struct sliccard *slic_card;
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struct physcard *phys_card;
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uint cardnuminuse[SLIC_MAX_CARDS];
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};
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struct slic_stats {
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/* xmit stats */
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u64 xmit_tcp_bytes;
|
||||
u64 xmit_tcp_segs;
|
||||
u64 xmit_bytes;
|
||||
u64 xmit_collisions;
|
||||
u64 xmit_unicasts;
|
||||
u64 xmit_other_error;
|
||||
u64 xmit_excess_collisions;
|
||||
/* rcv stats */
|
||||
u64 rcv_tcp_bytes;
|
||||
u64 rcv_tcp_segs;
|
||||
u64 rcv_bytes;
|
||||
u64 rcv_unicasts;
|
||||
u64 rcv_other_error;
|
||||
u64 rcv_drops;
|
||||
};
|
||||
|
||||
struct slic_shmem_data {
|
||||
u32 isr;
|
||||
u32 lnkstatus;
|
||||
struct slic_stats stats;
|
||||
};
|
||||
|
||||
struct slic_shmemory {
|
||||
dma_addr_t isr_phaddr;
|
||||
dma_addr_t lnkstatus_phaddr;
|
||||
dma_addr_t stats_phaddr;
|
||||
struct slic_shmem_data *shmem_data;
|
||||
};
|
||||
|
||||
struct slic_upr {
|
||||
uint adapter;
|
||||
u32 upr_request;
|
||||
u32 upr_data;
|
||||
u32 upr_data_h;
|
||||
u32 upr_buffer;
|
||||
u32 upr_buffer_h;
|
||||
struct slic_upr *next;
|
||||
};
|
||||
|
||||
struct slic_ifevents {
|
||||
uint oflow802;
|
||||
uint uflow802;
|
||||
uint tprtoflow;
|
||||
uint rcvearly;
|
||||
uint bufov;
|
||||
uint carre;
|
||||
uint longe;
|
||||
uint invp;
|
||||
uint crc;
|
||||
uint drbl;
|
||||
uint code;
|
||||
uint ip_hlen;
|
||||
uint ip_len;
|
||||
uint ip_csum;
|
||||
uint tp_csum;
|
||||
uint tp_hlen;
|
||||
};
|
||||
|
||||
struct adapter {
|
||||
void *ifp;
|
||||
struct sliccard *card;
|
||||
uint port;
|
||||
struct physcard *physcard;
|
||||
uint physport;
|
||||
uint cardindex;
|
||||
uint card_size;
|
||||
uint chipid;
|
||||
struct net_device *netdev;
|
||||
spinlock_t adapter_lock;
|
||||
spinlock_t reset_lock;
|
||||
struct pci_dev *pcidev;
|
||||
uint busnumber;
|
||||
uint slotnumber;
|
||||
uint functionnumber;
|
||||
ushort vendid;
|
||||
ushort devid;
|
||||
ushort subsysid;
|
||||
u32 irq;
|
||||
u32 drambase;
|
||||
u32 dramlength;
|
||||
uint queues_initialized;
|
||||
uint allocated;
|
||||
uint activated;
|
||||
u32 intrregistered;
|
||||
uint isp_initialized;
|
||||
uint gennumber;
|
||||
struct slic_shmemory shmem;
|
||||
dma_addr_t phys_shmem;
|
||||
void __iomem *regs;
|
||||
unsigned char state;
|
||||
unsigned char linkstate;
|
||||
unsigned char linkspeed;
|
||||
unsigned char linkduplex;
|
||||
uint flags;
|
||||
unsigned char macaddr[6];
|
||||
unsigned char currmacaddr[6];
|
||||
u32 macopts;
|
||||
ushort devflags_prev;
|
||||
u64 mcastmask;
|
||||
struct mcast_address *mcastaddrs;
|
||||
struct slic_upr *upr_list;
|
||||
uint upr_busy;
|
||||
struct timer_list pingtimer;
|
||||
u32 pingtimerset;
|
||||
struct timer_list loadtimer;
|
||||
u32 loadtimerset;
|
||||
spinlock_t upr_lock;
|
||||
spinlock_t bit64reglock;
|
||||
struct slic_rspqueue rspqueue;
|
||||
struct slic_rcvqueue rcvqueue;
|
||||
struct slic_cmdqueue cmdq_free;
|
||||
struct slic_cmdqueue cmdq_done;
|
||||
struct slic_cmdqueue cmdq_all;
|
||||
struct slic_cmdqmem cmdqmem;
|
||||
/*
|
||||
* SLIC Handles
|
||||
*/
|
||||
/* Object handles*/
|
||||
struct slic_handle slic_handles[SLIC_CMDQ_MAXCMDS + 1];
|
||||
/* Free object handles*/
|
||||
struct slic_handle *pfree_slic_handles;
|
||||
/* Object handle list lock*/
|
||||
spinlock_t handle_lock;
|
||||
ushort slic_handle_ix;
|
||||
|
||||
u32 xmitq_full;
|
||||
u32 all_reg_writes;
|
||||
u32 icr_reg_writes;
|
||||
u32 isr_reg_writes;
|
||||
u32 error_interrupts;
|
||||
u32 error_rmiss_interrupts;
|
||||
u32 rx_errors;
|
||||
u32 rcv_drops;
|
||||
u32 rcv_interrupts;
|
||||
u32 xmit_interrupts;
|
||||
u32 linkevent_interrupts;
|
||||
u32 upr_interrupts;
|
||||
u32 num_isrs;
|
||||
u32 false_interrupts;
|
||||
u32 tx_packets;
|
||||
u32 xmit_completes;
|
||||
u32 tx_drops;
|
||||
u32 rcv_broadcasts;
|
||||
u32 rcv_multicasts;
|
||||
u32 rcv_unicasts;
|
||||
u32 max_isr_rcvs;
|
||||
u32 max_isr_xmits;
|
||||
u32 rcv_interrupt_yields;
|
||||
u32 intagg_period;
|
||||
u32 intagg_delay;
|
||||
u32 dynamic_intagg;
|
||||
struct inicpm_state *inicpm_info;
|
||||
void *pinicpm_info;
|
||||
struct slic_ifevents if_events;
|
||||
struct slic_stats inicstats_prev;
|
||||
struct slicnet_stats slic_stats;
|
||||
};
|
||||
|
||||
static inline u32 slic_read32(struct adapter *adapter, unsigned int reg)
|
||||
{
|
||||
return ioread32(adapter->regs + reg);
|
||||
}
|
||||
|
||||
static inline void slic_write32(struct adapter *adapter, unsigned int reg,
|
||||
u32 val)
|
||||
{
|
||||
iowrite32(val, adapter->regs + reg);
|
||||
}
|
||||
|
||||
static inline void slic_write64(struct adapter *adapter, unsigned int reg,
|
||||
u32 val, u32 hiaddr)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&adapter->bit64reglock, flags);
|
||||
slic_write32(adapter, SLIC_REG_ADDR_UPPER, hiaddr);
|
||||
slic_write32(adapter, reg, val);
|
||||
mmiowb();
|
||||
spin_unlock_irqrestore(&adapter->bit64reglock, flags);
|
||||
}
|
||||
|
||||
static inline void slic_flush_write(struct adapter *adapter)
|
||||
{
|
||||
ioread32(adapter->regs + SLIC_REG_HOSTID);
|
||||
}
|
||||
|
||||
#if BITS_PER_LONG == 64
|
||||
#define SLIC_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & \
|
||||
0x00000000FFFFFFFF)
|
||||
#define SLIC_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & \
|
||||
0x00000000FFFFFFFF)
|
||||
#elif BITS_PER_LONG == 32
|
||||
#define SLIC_GET_ADDR_LOW(_addr) (u32)(_addr)
|
||||
#define SLIC_GET_ADDR_HIGH(_addr) (u32)0
|
||||
#else
|
||||
#error BITS_PER_LONG must be 32 or 64
|
||||
#endif
|
||||
|
||||
#define FLUSH true
|
||||
#define DONT_FLUSH false
|
||||
|
||||
#define SIOCSLICSETINTAGG (SIOCDEVPRIVATE + 10)
|
||||
|
||||
#endif /* __SLIC_DRIVER_H__ */
|
||||
|
|
@ -1,652 +0,0 @@
|
|||
/**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above
|
||||
* copyright notice, this list of conditions and the following
|
||||
* disclaimer in the documentation and/or other materials provided
|
||||
* with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
|
||||
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
|
||||
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
|
||||
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* The views and conclusions contained in the software and documentation
|
||||
* are those of the authors and should not be interpreted as representing
|
||||
* official policies, either expressed or implied, of Alacritech, Inc.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/*
|
||||
* FILENAME: slichw.h
|
||||
*
|
||||
* This header file contains definitions that are common to our hardware.
|
||||
*/
|
||||
#ifndef __SLICHW_H__
|
||||
#define __SLICHW_H__
|
||||
|
||||
#define PCI_VENDOR_ID_ALACRITECH 0x139A
|
||||
#define SLIC_1GB_DEVICE_ID 0x0005
|
||||
#define SLIC_2GB_DEVICE_ID 0x0007 /* Oasis Device ID */
|
||||
|
||||
#define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
|
||||
|
||||
#define SLIC_NBR_MACS 4
|
||||
|
||||
#define SLIC_RCVBUF_SIZE 2048
|
||||
#define SLIC_RCVBUF_HEADSIZE 34
|
||||
#define SLIC_RCVBUF_TAILSIZE 0
|
||||
#define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - \
|
||||
(SLIC_RCVBUF_HEADSIZE + \
|
||||
SLIC_RCVBUF_TAILSIZE))
|
||||
|
||||
#define VGBSTAT_XPERR 0x40000000
|
||||
#define VGBSTAT_XERRSHFT 25
|
||||
#define VGBSTAT_XCSERR 0x23
|
||||
#define VGBSTAT_XUFLOW 0x22
|
||||
#define VGBSTAT_XHLEN 0x20
|
||||
#define VGBSTAT_NETERR 0x01000000
|
||||
#define VGBSTAT_NERRSHFT 16
|
||||
#define VGBSTAT_NERRMSK 0x1ff
|
||||
#define VGBSTAT_NCSERR 0x103
|
||||
#define VGBSTAT_NUFLOW 0x102
|
||||
#define VGBSTAT_NHLEN 0x100
|
||||
#define VGBSTAT_LNKERR 0x00000080
|
||||
#define VGBSTAT_LERRMSK 0xff
|
||||
#define VGBSTAT_LDEARLY 0x86
|
||||
#define VGBSTAT_LBOFLO 0x85
|
||||
#define VGBSTAT_LCODERR 0x84
|
||||
#define VGBSTAT_LDBLNBL 0x83
|
||||
#define VGBSTAT_LCRCERR 0x82
|
||||
#define VGBSTAT_LOFLO 0x81
|
||||
#define VGBSTAT_LUFLO 0x80
|
||||
#define IRHDDR_FLEN_MSK 0x0000ffff
|
||||
#define IRHDDR_SVALID 0x80000000
|
||||
#define IRHDDR_ERR 0x10000000
|
||||
#define VRHSTAT_802OE 0x80000000
|
||||
#define VRHSTAT_TPOFLO 0x10000000
|
||||
#define VRHSTATB_802UE 0x80000000
|
||||
#define VRHSTATB_RCVE 0x40000000
|
||||
#define VRHSTATB_BUFF 0x20000000
|
||||
#define VRHSTATB_CARRE 0x08000000
|
||||
#define VRHSTATB_LONGE 0x02000000
|
||||
#define VRHSTATB_PREA 0x01000000
|
||||
#define VRHSTATB_CRC 0x00800000
|
||||
#define VRHSTATB_DRBL 0x00400000
|
||||
#define VRHSTATB_CODE 0x00200000
|
||||
#define VRHSTATB_TPCSUM 0x00100000
|
||||
#define VRHSTATB_TPHLEN 0x00080000
|
||||
#define VRHSTATB_IPCSUM 0x00040000
|
||||
#define VRHSTATB_IPLERR 0x00020000
|
||||
#define VRHSTATB_IPHERR 0x00010000
|
||||
#define SLIC_MAX64_BCNT 23
|
||||
#define SLIC_MAX32_BCNT 26
|
||||
#define IHCMD_XMT_REQ 0x01
|
||||
#define IHFLG_IFSHFT 2
|
||||
#define SLIC_RSPBUF_SIZE 32
|
||||
|
||||
#define SLIC_RESET_MAGIC 0xDEAD
|
||||
#define ICR_INT_OFF 0
|
||||
#define ICR_INT_ON 1
|
||||
#define ICR_INT_MASK 2
|
||||
|
||||
#define ISR_ERR 0x80000000
|
||||
#define ISR_RCV 0x40000000
|
||||
#define ISR_CMD 0x20000000
|
||||
#define ISR_IO 0x60000000
|
||||
#define ISR_UPC 0x10000000
|
||||
#define ISR_LEVENT 0x08000000
|
||||
#define ISR_RMISS 0x02000000
|
||||
#define ISR_UPCERR 0x01000000
|
||||
#define ISR_XDROP 0x00800000
|
||||
#define ISR_UPCBSY 0x00020000
|
||||
#define ISR_EVMSK 0xffff0000
|
||||
#define ISR_PINGMASK 0x00700000
|
||||
#define ISR_PINGDSMASK 0x00710000
|
||||
#define ISR_UPCMASK 0x11000000
|
||||
#define SLIC_WCS_START 0x80000000
|
||||
#define SLIC_WCS_COMPARE 0x40000000
|
||||
#define SLIC_RCVWCS_BEGIN 0x40000000
|
||||
#define SLIC_RCVWCS_FINISH 0x80000000
|
||||
#define SLIC_PM_MAXPATTERNS 6
|
||||
#define SLIC_PM_PATTERNSIZE 128
|
||||
#define SLIC_PMCAPS_WAKEONLAN 0x00000001
|
||||
#define MIICR_REG_PCR 0x00000000
|
||||
#define MIICR_REG_4 0x00040000
|
||||
#define MIICR_REG_9 0x00090000
|
||||
#define MIICR_REG_16 0x00100000
|
||||
#define PCR_RESET 0x8000
|
||||
#define PCR_POWERDOWN 0x0800
|
||||
#define PCR_SPEED_100 0x2000
|
||||
#define PCR_SPEED_1000 0x0040
|
||||
#define PCR_AUTONEG 0x1000
|
||||
#define PCR_AUTONEG_RST 0x0200
|
||||
#define PCR_DUPLEX_FULL 0x0100
|
||||
#define PSR_LINKUP 0x0004
|
||||
|
||||
#define PAR_ADV100FD 0x0100
|
||||
#define PAR_ADV100HD 0x0080
|
||||
#define PAR_ADV10FD 0x0040
|
||||
#define PAR_ADV10HD 0x0020
|
||||
#define PAR_ASYMPAUSE 0x0C00
|
||||
#define PAR_802_3 0x0001
|
||||
|
||||
#define PAR_ADV1000XFD 0x0020
|
||||
#define PAR_ADV1000XHD 0x0040
|
||||
#define PAR_ASYMPAUSE_FIBER 0x0180
|
||||
|
||||
#define PGC_ADV1000FD 0x0200
|
||||
#define PGC_ADV1000HD 0x0100
|
||||
#define SEEQ_LINKFAIL 0x4000
|
||||
#define SEEQ_SPEED 0x0080
|
||||
#define SEEQ_DUPLEX 0x0040
|
||||
#define TDK_DUPLEX 0x0800
|
||||
#define TDK_SPEED 0x0400
|
||||
#define MRV_REG16_XOVERON 0x0068
|
||||
#define MRV_REG16_XOVEROFF 0x0008
|
||||
#define MRV_SPEED_1000 0x8000
|
||||
#define MRV_SPEED_100 0x4000
|
||||
#define MRV_SPEED_10 0x0000
|
||||
#define MRV_FULLDUPLEX 0x2000
|
||||
#define MRV_LINKUP 0x0400
|
||||
|
||||
#define GIG_LINKUP 0x0001
|
||||
#define GIG_FULLDUPLEX 0x0002
|
||||
#define GIG_SPEED_MASK 0x000C
|
||||
#define GIG_SPEED_1000 0x0008
|
||||
#define GIG_SPEED_100 0x0004
|
||||
#define GIG_SPEED_10 0x0000
|
||||
|
||||
#define MCR_RESET 0x80000000
|
||||
#define MCR_CRCEN 0x40000000
|
||||
#define MCR_FULLD 0x10000000
|
||||
#define MCR_PAD 0x02000000
|
||||
#define MCR_RETRYLATE 0x01000000
|
||||
#define MCR_BOL_SHIFT 21
|
||||
#define MCR_IPG1_SHIFT 14
|
||||
#define MCR_IPG2_SHIFT 7
|
||||
#define MCR_IPG3_SHIFT 0
|
||||
#define GMCR_RESET 0x80000000
|
||||
#define GMCR_GBIT 0x20000000
|
||||
#define GMCR_FULLD 0x10000000
|
||||
#define GMCR_GAPBB_SHIFT 14
|
||||
#define GMCR_GAPR1_SHIFT 7
|
||||
#define GMCR_GAPR2_SHIFT 0
|
||||
#define GMCR_GAPBB_1000 0x60
|
||||
#define GMCR_GAPR1_1000 0x2C
|
||||
#define GMCR_GAPR2_1000 0x40
|
||||
#define GMCR_GAPBB_100 0x70
|
||||
#define GMCR_GAPR1_100 0x2C
|
||||
#define GMCR_GAPR2_100 0x40
|
||||
#define XCR_RESET 0x80000000
|
||||
#define XCR_XMTEN 0x40000000
|
||||
#define XCR_PAUSEEN 0x20000000
|
||||
#define XCR_LOADRNG 0x10000000
|
||||
#define RCR_RESET 0x80000000
|
||||
#define RCR_RCVEN 0x40000000
|
||||
#define RCR_RCVALL 0x20000000
|
||||
#define RCR_RCVBAD 0x10000000
|
||||
#define RCR_CTLEN 0x08000000
|
||||
#define RCR_ADDRAEN 0x02000000
|
||||
#define GXCR_RESET 0x80000000
|
||||
#define GXCR_XMTEN 0x40000000
|
||||
#define GXCR_PAUSEEN 0x20000000
|
||||
#define GRCR_RESET 0x80000000
|
||||
#define GRCR_RCVEN 0x40000000
|
||||
#define GRCR_RCVALL 0x20000000
|
||||
#define GRCR_RCVBAD 0x10000000
|
||||
#define GRCR_CTLEN 0x08000000
|
||||
#define GRCR_ADDRAEN 0x02000000
|
||||
#define GRCR_HASHSIZE_SHIFT 17
|
||||
#define GRCR_HASHSIZE 14
|
||||
|
||||
#define SLIC_EEPROM_ID 0xA5A5
|
||||
#define SLIC_SRAM_SIZE2GB (64 * 1024)
|
||||
#define SLIC_SRAM_SIZE1GB (32 * 1024)
|
||||
#define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
|
||||
#define SLIC_NBR_MACS 4
|
||||
|
||||
struct slic_rcvbuf {
|
||||
u8 pad1[6];
|
||||
u16 pad2;
|
||||
u32 pad3;
|
||||
u32 pad4;
|
||||
u32 buffer;
|
||||
u32 length;
|
||||
u32 status;
|
||||
u32 pad5;
|
||||
u16 pad6;
|
||||
u8 data[SLIC_RCVBUF_DATASIZE];
|
||||
};
|
||||
|
||||
struct slic_hddr_wds {
|
||||
union {
|
||||
struct {
|
||||
u32 frame_status;
|
||||
u32 frame_status_b;
|
||||
u32 time_stamp;
|
||||
u32 checksum;
|
||||
} hdrs_14port;
|
||||
struct {
|
||||
u32 frame_status;
|
||||
u16 byte_cnt;
|
||||
u16 tp_chksum;
|
||||
u16 ctx_hash;
|
||||
u16 mac_hash;
|
||||
u32 buf_lnk;
|
||||
} hdrs_gbit;
|
||||
} u0;
|
||||
};
|
||||
|
||||
#define frame_status14 u0.hdrs_14port.frame_status
|
||||
#define frame_status_b14 u0.hdrs_14port.frame_status_b
|
||||
#define frame_status_gb u0.hdrs_gbit.frame_status
|
||||
|
||||
struct slic_host64sg {
|
||||
u32 paddrl;
|
||||
u32 paddrh;
|
||||
u32 length;
|
||||
};
|
||||
|
||||
struct slic_host64_cmd {
|
||||
u32 hosthandle;
|
||||
u32 RSVD;
|
||||
u8 command;
|
||||
u8 flags;
|
||||
union {
|
||||
u16 rsv1;
|
||||
u16 rsv2;
|
||||
} u0;
|
||||
union {
|
||||
struct {
|
||||
u32 totlen;
|
||||
struct slic_host64sg bufs[SLIC_MAX64_BCNT];
|
||||
} slic_buffers;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct slic_rspbuf {
|
||||
u32 hosthandle;
|
||||
u32 pad0;
|
||||
u32 pad1;
|
||||
u32 status;
|
||||
u32 pad2[4];
|
||||
};
|
||||
|
||||
/* Reset Register */
|
||||
#define SLIC_REG_RESET 0x0000
|
||||
/* Interrupt Control Register */
|
||||
#define SLIC_REG_ICR 0x0008
|
||||
/* Interrupt status pointer */
|
||||
#define SLIC_REG_ISP 0x0010
|
||||
/* Interrupt status */
|
||||
#define SLIC_REG_ISR 0x0018
|
||||
/*
|
||||
* Header buffer address reg
|
||||
* 31-8 - phy addr of set of contiguous hdr buffers
|
||||
* 7-0 - number of buffers passed
|
||||
* Buffers are 256 bytes long on 256-byte boundaries.
|
||||
*/
|
||||
#define SLIC_REG_HBAR 0x0020
|
||||
/*
|
||||
* Data buffer handle & address reg
|
||||
* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page.
|
||||
*/
|
||||
#define SLIC_REG_DBAR 0x0028
|
||||
/*
|
||||
* Xmt Cmd buf addr regs.
|
||||
* 1 per XMT interface
|
||||
* 31-5 - phy addr of host command buffer
|
||||
* 4-0 - length of cmd in multiples of 32 bytes
|
||||
* Buffers are 32 bytes up to 512 bytes long
|
||||
*/
|
||||
#define SLIC_REG_CBAR 0x0030
|
||||
/* Write control store */
|
||||
#define SLIC_REG_WCS 0x0034
|
||||
/*
|
||||
* Response buffer address reg.
|
||||
* 31-8 - phy addr of set of contiguous response buffers
|
||||
* 7-0 - number of buffers passed
|
||||
* Buffers are 32 bytes long on 32-byte boundaries.
|
||||
*/
|
||||
#define SLIC_REG_RBAR 0x0038
|
||||
/* Read statistics (UPR) */
|
||||
#define SLIC_REG_RSTAT 0x0040
|
||||
/* Read link status */
|
||||
#define SLIC_REG_LSTAT 0x0048
|
||||
/* Write Mac Config */
|
||||
#define SLIC_REG_WMCFG 0x0050
|
||||
/* Write phy register */
|
||||
#define SLIC_REG_WPHY 0x0058
|
||||
/* Rcv Cmd buf addr reg */
|
||||
#define SLIC_REG_RCBAR 0x0060
|
||||
/* Read SLIC Config*/
|
||||
#define SLIC_REG_RCONFIG 0x0068
|
||||
/* Interrupt aggregation time */
|
||||
#define SLIC_REG_INTAGG 0x0070
|
||||
/* Write XMIT config reg */
|
||||
#define SLIC_REG_WXCFG 0x0078
|
||||
/* Write RCV config reg */
|
||||
#define SLIC_REG_WRCFG 0x0080
|
||||
/* Write rcv addr a low */
|
||||
#define SLIC_REG_WRADDRAL 0x0088
|
||||
/* Write rcv addr a high */
|
||||
#define SLIC_REG_WRADDRAH 0x0090
|
||||
/* Write rcv addr b low */
|
||||
#define SLIC_REG_WRADDRBL 0x0098
|
||||
/* Write rcv addr b high */
|
||||
#define SLIC_REG_WRADDRBH 0x00a0
|
||||
/* Low bits of mcast mask */
|
||||
#define SLIC_REG_MCASTLOW 0x00a8
|
||||
/* High bits of mcast mask */
|
||||
#define SLIC_REG_MCASTHIGH 0x00b0
|
||||
/* Ping the card */
|
||||
#define SLIC_REG_PING 0x00b8
|
||||
/* Dump command */
|
||||
#define SLIC_REG_DUMP_CMD 0x00c0
|
||||
/* Dump data pointer */
|
||||
#define SLIC_REG_DUMP_DATA 0x00c8
|
||||
/* Read card's pci_status register */
|
||||
#define SLIC_REG_PCISTATUS 0x00d0
|
||||
/* Write hostid field */
|
||||
#define SLIC_REG_WRHOSTID 0x00d8
|
||||
/* Put card in a low power state */
|
||||
#define SLIC_REG_LOW_POWER 0x00e0
|
||||
/* Force slic into quiescent state before soft reset */
|
||||
#define SLIC_REG_QUIESCE 0x00e8
|
||||
/* Reset interface queues */
|
||||
#define SLIC_REG_RESET_IFACE 0x00f0
|
||||
/*
|
||||
* Register is only written when it has changed.
|
||||
* Bits 63-32 for host i/f addrs.
|
||||
*/
|
||||
#define SLIC_REG_ADDR_UPPER 0x00f8
|
||||
/* 64 bit Header buffer address reg */
|
||||
#define SLIC_REG_HBAR64 0x0100
|
||||
/* 64 bit Data buffer handle & address reg */
|
||||
#define SLIC_REG_DBAR64 0x0108
|
||||
/* 64 bit Xmt Cmd buf addr regs. */
|
||||
#define SLIC_REG_CBAR64 0x0110
|
||||
/* 64 bit Response buffer address reg.*/
|
||||
#define SLIC_REG_RBAR64 0x0118
|
||||
/* 64 bit Rcv Cmd buf addr reg*/
|
||||
#define SLIC_REG_RCBAR64 0x0120
|
||||
/* Read statistics (64 bit UPR) */
|
||||
#define SLIC_REG_RSTAT64 0x0128
|
||||
/* Download Gigabit RCV sequencer ucode */
|
||||
#define SLIC_REG_RCV_WCS 0x0130
|
||||
/* Write VlanId field */
|
||||
#define SLIC_REG_WRVLANID 0x0138
|
||||
/* Read Transformer info */
|
||||
#define SLIC_REG_READ_XF_INFO 0x0140
|
||||
/* Write Transformer info */
|
||||
#define SLIC_REG_WRITE_XF_INFO 0x0148
|
||||
/* Write card ticks per second */
|
||||
#define SLIC_REG_TICKS_PER_SEC 0x0170
|
||||
|
||||
#define SLIC_REG_HOSTID 0x1554
|
||||
|
||||
enum UPR_REQUEST {
|
||||
SLIC_UPR_STATS,
|
||||
SLIC_UPR_RLSR,
|
||||
SLIC_UPR_WCFG,
|
||||
SLIC_UPR_RCONFIG,
|
||||
SLIC_UPR_RPHY,
|
||||
SLIC_UPR_ENLB,
|
||||
SLIC_UPR_ENCT,
|
||||
SLIC_UPR_PDWN,
|
||||
SLIC_UPR_PING,
|
||||
SLIC_UPR_DUMP,
|
||||
};
|
||||
|
||||
struct inicpm_wakepattern {
|
||||
u32 patternlength;
|
||||
u8 pattern[SLIC_PM_PATTERNSIZE];
|
||||
u8 mask[SLIC_PM_PATTERNSIZE];
|
||||
};
|
||||
|
||||
struct inicpm_state {
|
||||
u32 powercaps;
|
||||
u32 powerstate;
|
||||
u32 wake_linkstatus;
|
||||
u32 wake_magicpacket;
|
||||
u32 wake_framepattern;
|
||||
struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
|
||||
};
|
||||
|
||||
struct slicpm_packet_pattern {
|
||||
u32 priority;
|
||||
u32 reserved;
|
||||
u32 masksize;
|
||||
u32 patternoffset;
|
||||
u32 patternsize;
|
||||
u32 patternflags;
|
||||
};
|
||||
|
||||
enum slicpm_power_state {
|
||||
slicpm_state_unspecified = 0,
|
||||
slicpm_state_d0,
|
||||
slicpm_state_d1,
|
||||
slicpm_state_d2,
|
||||
slicpm_state_d3,
|
||||
slicpm_state_maximum
|
||||
};
|
||||
|
||||
struct slicpm_wakeup_capabilities {
|
||||
enum slicpm_power_state min_magic_packet_wakeup;
|
||||
enum slicpm_power_state min_pattern_wakeup;
|
||||
enum slicpm_power_state min_link_change_wakeup;
|
||||
};
|
||||
|
||||
struct slic_pnp_capabilities {
|
||||
u32 flags;
|
||||
struct slicpm_wakeup_capabilities wakeup_capabilities;
|
||||
};
|
||||
|
||||
struct slic_config_mac {
|
||||
u8 macaddr_a[6];
|
||||
};
|
||||
|
||||
#define ATK_FRU_FORMAT 0x00
|
||||
#define VENDOR1_FRU_FORMAT 0x01
|
||||
#define VENDOR2_FRU_FORMAT 0x02
|
||||
#define VENDOR3_FRU_FORMAT 0x03
|
||||
#define VENDOR4_FRU_FORMAT 0x04
|
||||
#define NO_FRU_FORMAT 0xFF
|
||||
|
||||
struct atk_fru {
|
||||
u8 assembly[6];
|
||||
u8 revision[2];
|
||||
u8 serial[14];
|
||||
u8 pad[3];
|
||||
};
|
||||
|
||||
struct vendor1_fru {
|
||||
u8 commodity;
|
||||
u8 assembly[4];
|
||||
u8 revision[2];
|
||||
u8 supplier[2];
|
||||
u8 date[2];
|
||||
u8 sequence[3];
|
||||
u8 pad[13];
|
||||
};
|
||||
|
||||
struct vendor2_fru {
|
||||
u8 part[8];
|
||||
u8 supplier[5];
|
||||
u8 date[3];
|
||||
u8 sequence[4];
|
||||
u8 pad[7];
|
||||
};
|
||||
|
||||
struct vendor3_fru {
|
||||
u8 assembly[6];
|
||||
u8 revision[2];
|
||||
u8 serial[14];
|
||||
u8 pad[3];
|
||||
};
|
||||
|
||||
struct vendor4_fru {
|
||||
u8 number[8];
|
||||
u8 part[8];
|
||||
u8 version[8];
|
||||
u8 pad[3];
|
||||
};
|
||||
|
||||
union oemfru {
|
||||
struct vendor1_fru vendor1_fru;
|
||||
struct vendor2_fru vendor2_fru;
|
||||
struct vendor3_fru vendor3_fru;
|
||||
struct vendor4_fru vendor4_fru;
|
||||
};
|
||||
|
||||
/*
|
||||
* SLIC EEPROM structure for Mojave
|
||||
*/
|
||||
struct slic_eeprom {
|
||||
u16 id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
|
||||
u16 eecode_size; /* 01 Size of EEPROM Codes (bytes * 4)*/
|
||||
u16 flash_size; /* 02 Flash size */
|
||||
u16 eeprom_size; /* 03 EEPROM Size */
|
||||
u16 vendor_id; /* 04 Vendor ID */
|
||||
u16 device_id; /* 05 Device ID */
|
||||
u8 revision_id; /* 06 Revision ID */
|
||||
u8 class_code[3]; /* 07 Class Code */
|
||||
u8 dbg_int_pin; /* 08 Debug Interrupt pin */
|
||||
u8 net_int_pin0; /* Network Interrupt Pin */
|
||||
u8 min_grant; /* 09 Minimum grant */
|
||||
u8 max_lat; /* Maximum Latency */
|
||||
u16 pci_status; /* 10 PCI Status */
|
||||
u16 sub_sys_vid; /* 11 Subsystem Vendor Id */
|
||||
u16 sub_sys_id; /* 12 Subsystem ID */
|
||||
u16 dbg_dev_id; /* 13 Debug Device Id */
|
||||
u16 dram_rom_fn; /* 14 Dram/Rom function */
|
||||
u16 dsize2pci; /* 15 DRAM size to PCI (bytes * 64K) */
|
||||
u16 rsize2pci; /* 16 ROM extension size to PCI (bytes * 4k) */
|
||||
u8 net_int_pin1; /* 17 Network Interface Pin 1
|
||||
* (simba/leone only)
|
||||
*/
|
||||
u8 net_int_pin2; /* Network Interface Pin 2 (simba/leone only)*/
|
||||
union {
|
||||
u8 net_int_pin3;/* 18 Network Interface Pin 3 (simba only) */
|
||||
u8 free_time; /* FreeTime setting (leone/mojave only) */
|
||||
} u1;
|
||||
u8 tbi_ctl; /* 10-bit interface control (Mojave only) */
|
||||
u16 dram_size; /* 19 DRAM size (bytes * 64k) */
|
||||
union {
|
||||
struct {
|
||||
/* Mac Interface Specific portions */
|
||||
struct slic_config_mac mac_info[SLIC_NBR_MACS];
|
||||
} mac; /* MAC access for all boards */
|
||||
struct {
|
||||
/* use above struct for MAC access */
|
||||
struct slic_config_mac pad[SLIC_NBR_MACS - 1];
|
||||
u16 device_id2; /* Device ID for 2nd PCI function */
|
||||
u8 int_pin2; /* Interrupt pin for 2nd PCI function */
|
||||
u8 class_code2[3]; /* Class Code for 2nd PCI function */
|
||||
} mojave; /* 2nd function access for gigabit board */
|
||||
} u2;
|
||||
u16 cfg_byte6; /* Config Byte 6 */
|
||||
u16 pme_capab; /* Power Mgment capabilities */
|
||||
u16 nw_clk_ctrls; /* NetworkClockControls */
|
||||
u8 fru_format; /* Alacritech FRU format type */
|
||||
struct atk_fru atk_fru; /* Alacritech FRU information */
|
||||
u8 oem_fru_format; /* optional OEM FRU format type */
|
||||
union oemfru oem_fru; /* optional OEM FRU information */
|
||||
u8 pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
|
||||
* (if OEM FRU info exists) and two unusable
|
||||
* bytes at the end
|
||||
*/
|
||||
};
|
||||
|
||||
/* SLIC EEPROM structure for Oasis */
|
||||
struct oslic_eeprom {
|
||||
u16 id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
|
||||
u16 eecode_size; /* 01 Size of EEPROM Codes (bytes * 4)*/
|
||||
u16 flash_config0; /* 02 Flash Config for SPI device 0 */
|
||||
u16 flash_config1; /* 03 Flash Config for SPI device 1 */
|
||||
u16 vendor_id; /* 04 Vendor ID */
|
||||
u16 device_id; /* 05 Device ID (function 0) */
|
||||
u8 revision_id; /* 06 Revision ID */
|
||||
u8 class_code[3]; /* 07 Class Code for PCI function 0 */
|
||||
u8 int_pin1; /* 08 Interrupt pin for PCI function 1*/
|
||||
u8 class_code2[3]; /* 09 Class Code for PCI function 1 */
|
||||
u8 int_pin2; /* 10 Interrupt pin for PCI function 2*/
|
||||
u8 int_pin0; /* Interrupt pin for PCI function 0*/
|
||||
u8 min_grant; /* 11 Minimum grant */
|
||||
u8 max_lat; /* Maximum Latency */
|
||||
u16 sub_sys_vid; /* 12 Subsystem Vendor Id */
|
||||
u16 sub_sys_id; /* 13 Subsystem ID */
|
||||
u16 flash_size; /* 14 Flash size (bytes / 4K) */
|
||||
u16 dsize2pci; /* 15 DRAM size to PCI (bytes / 64K) */
|
||||
u16 rsize2pci; /* 16 Flash (ROM extension) size to PCI
|
||||
* (bytes / 4K)
|
||||
*/
|
||||
u16 device_id1; /* 17 Device Id (function 1) */
|
||||
u16 device_id2; /* 18 Device Id (function 2) */
|
||||
u16 cfg_byte6; /* 19 Device Status Config Bytes 6-7 */
|
||||
u16 pme_capab; /* 20 Power Mgment capabilities */
|
||||
u8 msi_capab; /* 21 MSI capabilities */
|
||||
u8 clock_divider; /* Clock divider */
|
||||
u16 pci_status_low; /* 22 PCI Status bits 15:0 */
|
||||
u16 pci_status_high; /* 23 PCI Status bits 31:16 */
|
||||
u16 dram_config_low; /* 24 DRAM Configuration bits 15:0 */
|
||||
u16 dram_config_high; /* 25 DRAM Configuration bits 31:16 */
|
||||
u16 dram_size; /* 26 DRAM size (bytes / 64K) */
|
||||
u16 gpio_tbi_ctl; /* 27 GPIO/TBI controls for functions 1/0 */
|
||||
u16 eeprom_size; /* 28 EEPROM Size */
|
||||
struct slic_config_mac mac_info[2]; /* 29 MAC addresses (2 ports) */
|
||||
u8 fru_format; /* 35 Alacritech FRU format type */
|
||||
struct atk_fru atk_fru; /* Alacritech FRU information */
|
||||
u8 oem_fru_format; /* optional OEM FRU format type */
|
||||
union oemfru oem_fru; /* optional OEM FRU information */
|
||||
u8 pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
|
||||
* (if OEM FRU info exists) and two unusable
|
||||
* bytes at the end
|
||||
*/
|
||||
};
|
||||
|
||||
#define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
|
||||
#define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
|
||||
|
||||
/*
|
||||
* SLIC CONFIG structure
|
||||
*
|
||||
* This structure lives in the CARD structure and is valid for all board types.
|
||||
* It is filled in from the appropriate EEPROM structure by
|
||||
* SlicGetConfigData()
|
||||
*/
|
||||
struct slic_config {
|
||||
bool eeprom_valid; /* Valid EEPROM flag (checksum good?) */
|
||||
u16 dram_size; /* DRAM size (bytes / 64K) */
|
||||
struct slic_config_mac mac_info[SLIC_NBR_MACS]; /* MAC addresses */
|
||||
u8 fru_format; /* Alacritech FRU format type */
|
||||
struct atk_fru atk_fru; /* Alacritech FRU information */
|
||||
u8 oem_fru_format; /* optional OEM FRU format type */
|
||||
union {
|
||||
struct vendor1_fru vendor1_fru;
|
||||
struct vendor2_fru vendor2_fru;
|
||||
struct vendor3_fru vendor3_fru;
|
||||
struct vendor4_fru vendor4_fru;
|
||||
} oem_fru;
|
||||
};
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user