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IXP4xx: workaround for PCI prefetch problems near 64 MB boundary.

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Map unused registers at the end of DMA region at 64 MB to allow PCI masters
to cross the boundary when prefetching data from SDRAM.

Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
This commit is contained in:
Krzysztof Hałasa 2009-03-13 17:57:04 +01:00
parent fec6c6fec3
commit 0a07232ff6
2 changed files with 13 additions and 11 deletions
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1
arch/arm/include/asm/sizes.h
View File

@ -43,6 +43,7 @@
#define SZ_8M 0x00800000
#define SZ_16M 0x01000000
#define SZ_32M 0x02000000
#define SZ_48M 0x03000000
#define SZ_64M 0x04000000
#define SZ_128M 0x08000000
#define SZ_256M 0x10000000

23
arch/arm/mach-ixp4xx/common-pci.c
View File

@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size,
}
void __init ixp4xx_pci_preinit(void)
{
{
unsigned long cpuid = read_cpuid_id();
/*
@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void)
pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n");
/*
/*
* We use identity AHB->PCI address translation
* in the 0x48000000 to 0x4bffffff address space
*/
*PCI_PCIMEMBASE = 0x48494A4B;
/*
/*
* We also use identity PCI->AHB address translation
* in 4 16MB BARs that begin at the physical memory start
*/
*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
*PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) +
((PHYS_OFFSET & 0xFF000000) >> 8) +
((PHYS_OFFSET & 0xFF000000) >> 16) +
((PHYS_OFFSET & 0xFF000000) >> 24) +
@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void)
pr_debug("setup BARs in controller\n");
/*
* We configure the PCI inbound memory windows to be
* We configure the PCI inbound memory windows to be
* 1:1 mapped to SDRAM
*/
local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000);
local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000);
local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000);
local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000);
local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET);
local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M);
local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M);
local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M);
/*
* Enable CSR window at 0xff000000.
* Enable CSR window at 64 MiB to allow PCI masters
* to continue prefetching past 64 MiB boundary.
*/
local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008);
local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M);
/*
* Enable the IO window to be way up high, at 0xfffffc00