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pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
[takeshi.kihara.df: add blank lines after function declarations]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Takeshi Kihara
Geert Uytterhoeven
parent
f05603fa6a
commit
0a042b355e
@ -558,6 +558,9 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
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FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
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FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
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#define PINMUX_PHYS \
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FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
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enum {
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PINMUX_RESERVED = 0,
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@ -583,6 +586,7 @@ enum {
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PINMUX_IPSR
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PINMUX_MOD_SELS
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PINMUX_STATIC
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PINMUX_PHYS
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PINMUX_MARK_END,
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#undef F_
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#undef FM
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@ -620,13 +624,15 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
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PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
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PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
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PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
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PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
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PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
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PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
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PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
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PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
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PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
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PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
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PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
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@ -679,14 +685,16 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
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PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
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PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
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PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
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PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
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PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
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PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
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PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
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PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
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PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
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PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
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PINMUX_IPSR_GPSR(IP1_31_28, A0),
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PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
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@ -1120,13 +1128,15 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
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PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
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PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
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PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
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PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
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PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDF_0),
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PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
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PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
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PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
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PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
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PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
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PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
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@ -1494,11 +1504,6 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
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PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
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/* I2C */
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PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
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PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
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PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
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/*
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* Static pins can not be muxed between different functions but
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* still need mark entries in the pinmux list. Add each static
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@ -2478,52 +2483,92 @@ static const unsigned int hscif4_data_b_mux[] = {
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};
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/* - I2C -------------------------------------------------------------------- */
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static const unsigned int i2c0_pins[] = {
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/* SCL, SDA */
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RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
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};
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static const unsigned int i2c0_mux[] = {
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SCL0_MARK, SDA0_MARK,
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};
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static const unsigned int i2c1_a_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
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};
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static const unsigned int i2c1_a_mux[] = {
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SDA1_A_MARK, SCL1_A_MARK,
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};
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static const unsigned int i2c1_b_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
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};
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static const unsigned int i2c1_b_mux[] = {
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SDA1_B_MARK, SCL1_B_MARK,
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};
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static const unsigned int i2c2_a_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
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};
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static const unsigned int i2c2_a_mux[] = {
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SDA2_A_MARK, SCL2_A_MARK,
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};
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static const unsigned int i2c2_b_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
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};
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static const unsigned int i2c2_b_mux[] = {
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SDA2_B_MARK, SCL2_B_MARK,
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};
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static const unsigned int i2c3_pins[] = {
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/* SCL, SDA */
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RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
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};
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static const unsigned int i2c3_mux[] = {
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SCL3_MARK, SDA3_MARK,
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};
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static const unsigned int i2c5_pins[] = {
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/* SCL, SDA */
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RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
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};
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static const unsigned int i2c5_mux[] = {
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SCL5_MARK, SDA5_MARK,
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};
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static const unsigned int i2c6_a_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
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};
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static const unsigned int i2c6_a_mux[] = {
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SDA6_A_MARK, SCL6_A_MARK,
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};
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static const unsigned int i2c6_b_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
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};
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static const unsigned int i2c6_b_mux[] = {
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SDA6_B_MARK, SCL6_B_MARK,
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};
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static const unsigned int i2c6_c_pins[] = {
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/* SDA, SCL */
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RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
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};
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static const unsigned int i2c6_c_mux[] = {
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SDA6_C_MARK, SCL6_C_MARK,
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};
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@ -4413,10 +4458,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
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SH_PFC_PIN_GROUP(hscif4_clk),
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SH_PFC_PIN_GROUP(hscif4_ctrl),
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SH_PFC_PIN_GROUP(hscif4_data_b),
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SH_PFC_PIN_GROUP(i2c0),
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SH_PFC_PIN_GROUP(i2c1_a),
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SH_PFC_PIN_GROUP(i2c1_b),
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SH_PFC_PIN_GROUP(i2c2_a),
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SH_PFC_PIN_GROUP(i2c2_b),
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SH_PFC_PIN_GROUP(i2c3),
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SH_PFC_PIN_GROUP(i2c5),
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SH_PFC_PIN_GROUP(i2c6_a),
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SH_PFC_PIN_GROUP(i2c6_b),
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SH_PFC_PIN_GROUP(i2c6_c),
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@ -4807,6 +4855,10 @@ static const char * const hscif4_groups[] = {
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"hscif4_data_b",
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};
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static const char * const i2c0_groups[] = {
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"i2c0",
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};
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static const char * const i2c1_groups[] = {
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"i2c1_a",
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"i2c1_b",
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@ -4817,6 +4869,14 @@ static const char * const i2c2_groups[] = {
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"i2c2_b",
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};
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static const char * const i2c3_groups[] = {
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"i2c3",
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};
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static const char * const i2c5_groups[] = {
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"i2c5",
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};
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static const char * const i2c6_groups[] = {
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"i2c6_a",
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"i2c6_b",
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@ -5166,8 +5226,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
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SH_PFC_FUNCTION(hscif2),
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SH_PFC_FUNCTION(hscif3),
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SH_PFC_FUNCTION(hscif4),
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SH_PFC_FUNCTION(i2c0),
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SH_PFC_FUNCTION(i2c1),
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SH_PFC_FUNCTION(i2c2),
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SH_PFC_FUNCTION(i2c3),
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SH_PFC_FUNCTION(i2c5),
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SH_PFC_FUNCTION(i2c6),
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SH_PFC_FUNCTION(intc_ex),
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SH_PFC_FUNCTION(msiof0),
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