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ARM: OMAP: Add OMAP chip type structure; clean up mach-omap2/id.c
Add a new OMAP chip identification interface, omap_chip_id. omap_chip_id is a structure which contains one bit for each OMAP2/3 CPU type, and on 3430, ES level. For example, the CHIP_IS_OMAP2420 bit is set in omap_chip at boot on an OMAP2420. On OMAP3430ES2, both CHIP_IS_OMAP3430 and CHIP_IS_OMAP3430ES2 bits are set. omap_chip is set in mach-omap2/id.c by _set_omap_chip(). Other code should use the omap_chip_is() function to test against omap_chip. Also, clean up id.c by splitting some code out of omap_check_revision() into its own function, _set_system_rev(); and converting some debug printk()s into pr_debug(). Second revision. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Paul Walmsley
Tony Lindgren
parent
ff00fcc9ca
commit
097c584cd4
@ -17,16 +17,23 @@
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#include <asm/io.h>
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#if defined(CONFIG_ARCH_OMAP2420)
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#define OMAP24XX_TAP_BASE io_p2v(0x48014000)
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#endif
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#include <asm/arch/control.h>
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#include <asm/arch/cpu.h>
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#if defined(CONFIG_ARCH_OMAP2430)
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#define OMAP24XX_TAP_BASE io_p2v(0x4900A000)
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#if defined(CONFIG_ARCH_OMAP2420)
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#define TAP_BASE io_p2v(0x48014000)
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#elif defined(CONFIG_ARCH_OMAP2430)
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#define TAP_BASE io_p2v(0x4900A000)
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#elif defined(CONFIG_ARCH_OMAP34XX)
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#define TAP_BASE io_p2v(0x4830A000)
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#endif
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#define OMAP_TAP_IDCODE 0x0204
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#if defined(CONFIG_ARCH_OMAP34XX)
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#define OMAP_TAP_PROD_ID 0x0210
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#else
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#define OMAP_TAP_PROD_ID 0x0208
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#endif
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#define OMAP_TAP_DIE_ID_0 0x0218
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#define OMAP_TAP_DIE_ID_1 0x021C
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@ -56,9 +63,134 @@ static struct omap_id omap_ids[] __initdata = {
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{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
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};
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static struct omap_chip_id omap_chip;
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/**
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* omap_chip_is - test whether currently running OMAP matches a chip type
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* @oc: omap_chip_t to test against
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*
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* Test whether the currently-running OMAP chip matches the supplied
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* chip type 'oc'. Returns 1 upon a match; 0 upon failure.
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*/
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int omap_chip_is(struct omap_chip_id oci)
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{
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return (oci.oc & omap_chip.oc) ? 1 : 0;
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}
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EXPORT_SYMBOL(omap_chip_is);
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static u32 __init read_tap_reg(int reg)
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{
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return __raw_readl(OMAP24XX_TAP_BASE + reg);
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unsigned int regval = 0;
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u32 cpuid;
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/* Reading the IDCODE register on 3430 ES1 results in a
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* data abort as the register is not exposed on the OCP
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* Hence reading the Cortex Rev
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*/
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cpuid = read_cpuid(CPUID_ID);
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/* If the processor type is Cortex-A8 and the revision is 0x0
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* it means its Cortex r0p0 which is 3430 ES1
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*/
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if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
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switch (reg) {
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case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
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/* Making DevType as 0xF in ES1 to differ from ES2 */
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case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
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case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
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case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
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case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
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case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
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}
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} else
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regval = __raw_readl(TAP_BASE + reg);
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return regval;
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}
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/*
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* _set_system_rev - set the system_rev global based on current OMAP chip type
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*
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* Set the system_rev global. This is primarily used by the cpu_is_omapxxxx()
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* macros.
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*/
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static void __init _set_system_rev(u32 type, u8 rev)
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{
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u32 i, ctrl_status;
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/*
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* system_rev encoding is as follows
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* system_rev & 0xff000000 -> Omap Class (24xx/34xx)
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* system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
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* system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
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* system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
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* system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
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* system_rev & 0x000000c0 -> IDCODE revision[6:7]
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* system_rev & 0x0000003f -> sys_boot[0:5]
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*/
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/* Embedding the ES revision info in type field */
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system_rev = type;
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/* Also add IDCODE revision info only two lower bits */
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system_rev |= ((rev & 0x3) << 6);
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/* Add in the device type and sys_boot fields (see above) */
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if (cpu_is_omap24xx()) {
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i = OMAP24XX_CONTROL_STATUS;
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} else if (cpu_is_omap343x()) {
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i = OMAP343X_CONTROL_STATUS;
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} else {
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printk(KERN_ERR "id: unknown CPU type\n");
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BUG();
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}
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ctrl_status = omap_ctrl_readl(i);
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system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
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OMAP2_SYSBOOT_4_MASK |
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OMAP2_SYSBOOT_3_MASK |
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OMAP2_SYSBOOT_2_MASK |
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OMAP2_SYSBOOT_1_MASK |
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OMAP2_SYSBOOT_0_MASK));
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system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
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}
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/*
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* _set_omap_chip - set the omap_chip global based on OMAP chip type
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*
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* Build the omap_chip bits. This variable is used by powerdomain and
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* clockdomain code to indicate whether structures are applicable for
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* the current OMAP chip type by ANDing it against a 'platform' bitfield
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* in the structure.
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*/
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static void __init _set_omap_chip(void)
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{
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if (cpu_is_omap343x()) {
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omap_chip.oc = CHIP_IS_OMAP3430;
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if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
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omap_chip.oc |= CHIP_IS_OMAP3430ES1;
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else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
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omap_chip.oc |= CHIP_IS_OMAP3430ES2;
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} else if (cpu_is_omap243x()) {
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/* Currently only supports 2430ES2.1 and 2430-all */
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omap_chip.oc |= CHIP_IS_OMAP2430;
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} else if (cpu_is_omap242x()) {
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/* Currently only supports 2420ES2.1.1 and 2420-all */
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omap_chip.oc |= CHIP_IS_OMAP2420;
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} else {
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/* Current CPU not supported by this code. */
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printk(KERN_WARNING "OMAP chip type code does not yet support "
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"this CPU type.\n");
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WARN_ON(1);
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}
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}
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void __init omap2_check_revision(void)
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@ -76,21 +208,31 @@ void __init omap2_check_revision(void)
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rev = (idcode >> 28) & 0x0f;
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dev_type = (prod_id >> 16) & 0x0f;
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#ifdef DEBUG
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printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
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idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
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printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_0));
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printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
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read_tap_reg(OMAP_TAP_DIE_ID_1),
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(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
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printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_2));
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printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_3));
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printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
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prod_id, dev_type);
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#endif
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pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
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idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
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pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_0));
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pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
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read_tap_reg(OMAP_TAP_DIE_ID_1),
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(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
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pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_2));
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pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
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read_tap_reg(OMAP_TAP_DIE_ID_3));
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pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
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prod_id, dev_type);
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/*
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* Detection for 34xx ES2.0 and above can be done with just
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* hawkeye and rev. See TRM 1.5.2 Device Identification.
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* Note that rev cannot be used directly as ES1.0 uses value 0.
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*/
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if (hawkeye == 0xb7ae) {
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system_rev = 0x34300000 | ((1 + rev) << 12);
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pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
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_set_omap_chip();
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return;
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}
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/* Check hawkeye ids */
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for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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@ -114,16 +256,15 @@ void __init omap2_check_revision(void)
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omap_ids[i].type >> 16);
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j = i;
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}
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system_rev = omap_ids[j].type;
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system_rev |= rev << 8;
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_set_system_rev(omap_ids[j].type, rev);
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/* Add the cpu class info (24xx) */
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system_rev |= 0x24;
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_set_omap_chip();
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pr_info("OMAP%04x", system_rev >> 16);
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if ((system_rev >> 8) & 0x0f)
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printk("%x", (system_rev >> 8) & 0x0f);
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printk("\n");
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pr_info("ES%x", (system_rev >> 12) & 0xf);
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pr_info("\n");
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}
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@ -3,7 +3,7 @@
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*
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* OMAP cpu type detection
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*
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* Copyright (C) 2004 Nokia Corporation
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* Copyright (C) 2004, 2008 Nokia Corporation
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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@ -26,6 +26,12 @@
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#ifndef __ASM_ARCH_OMAP_CPU_H
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#define __ASM_ARCH_OMAP_CPU_H
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struct omap_chip_id {
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u8 oc;
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};
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#define OMAP_CHIP_INIT(x) { .oc = x }
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extern unsigned int system_rev;
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#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
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@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
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#define OMAP2430_REV_ES1_0 0x24300000
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#define OMAP3430_REV_ES1_0 0x34300000
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#define OMAP3430_REV_ES2_0 0x34301000
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#define OMAP3430_REV_ES2_1 0x34302000
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#define OMAP3430_REV_ES2_2 0x34303000
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/*
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* omap_chip bits
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*
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* CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
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* valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
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* something that is only valid on that particular ES revision.
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*
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* These bits may be ORed together to indicate structures that are
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* available on multiple chip types.
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*
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* To test whether a particular structure matches the current OMAP chip type,
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* use omap_chip_is().
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*
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*/
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#define CHIP_IS_OMAP2420 (1 << 0)
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#define CHIP_IS_OMAP2430 (1 << 1)
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#define CHIP_IS_OMAP3430 (1 << 2)
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#define CHIP_IS_OMAP3430ES1 (1 << 3)
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#define CHIP_IS_OMAP3430ES2 (1 << 4)
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#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
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int omap_chip_is(struct omap_chip_id oci);
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/*
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* Macro to detect device type i.e. EMU/HS/TST/GP/BAD
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@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
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#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
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#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
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#endif
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void omap2_check_revision(void);
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#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
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#endif
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