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net: phy: microchip_t1: Adds support for lan887x phy
The LAN887x is a Single-Port Ethernet Physical Layer Transceiver compliant with the IEEE 802.3bw (100BASE-T1) and IEEE 802.3bp (1000BASE-T1) specifications. The device provides 100/1000 Mbit/s transmit and receive capability over a single Unshielded Twisted Pair (UTP) cable. It supports communication with an Ethernet MAC via standard RGMII/SGMII interfaces. LAN887x supports following features, - Events/Interrupts - LED/GPIO Operation - IEEE 1588 (PTP) - SQI - Sleep and Wakeup (TC10) - Cable Diagnostics First patch only supports 100Mbps and 1000Mbps force-mode. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Divya Koppera <divya.koppera@microchip.com> Link: https://patch.msgid.link/20240821055906.27717-3-Divya.Koppera@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Divya Koppera
Jakub Kicinski
parent
d4c897675a
commit
0941c83282
@ -12,6 +12,7 @@
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#define PHY_ID_LAN87XX 0x0007c150
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#define PHY_ID_LAN937X 0x0007c180
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#define PHY_ID_LAN887X 0x0007c1f0
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/* External Register Control Register */
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#define LAN87XX_EXT_REG_CTL (0x14)
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@ -94,8 +95,101 @@
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/* SQI defines */
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#define LAN87XX_MAX_SQI 0x07
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/* Chiptop registers */
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#define LAN887X_PMA_EXT_ABILITY_2 0x12
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#define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1)
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#define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)
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/* DSP 100M registers */
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#define LAN887x_CDR_CONFIG1_100 0x0405
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#define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411
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#define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417
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#define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c
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#define LAN887x_PROT_DISABLE_100 0x0425
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#define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454
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/* DSP 1000M registers */
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#define LAN887X_LOCK1_EQLSR_CONFIG 0x0811
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#define LAN887X_LOCK3_EQLSR_CONFIG 0x0813
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#define LAN887X_PROT_DISABLE 0x0825
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#define LAN887X_FFE_GAIN6 0x0843
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#define LAN887X_FFE_GAIN7 0x0844
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#define LAN887X_FFE_GAIN8 0x0845
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#define LAN887X_FFE_GAIN9 0x0846
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#define LAN887X_ECHO_DELAY_CONFIG 0x08ec
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#define LAN887X_FFE_MAX_CONFIG 0x08ee
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/* PCS 1000M registers */
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#define LAN887X_SCR_CONFIG_3 0x8043
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#define LAN887X_INFO_FLD_CONFIG_5 0x8048
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/* T1 afe registers */
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#define LAN887X_ZQCAL_CONTROL_1 0x8080
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#define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089
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#define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b
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#define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d
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#define LAN887X_TX_AMPLT_1000T1_REG 0x80b0
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#define LAN887X_INIT_COEFF_DFE1_100 0x0422
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/* PMA registers */
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#define LAN887X_DSP_PMA_CONTROL 0x810e
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#define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4)
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/* PCS 100M registers */
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#define LAN887X_IDLE_ERR_TIMER_WIN 0x8204
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#define LAN887X_IDLE_ERR_CNT_THRESH 0x8213
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/* Misc registers */
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#define LAN887X_REG_REG26 0x001a
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#define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8)
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/* Mis registers */
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#define LAN887X_MIS_CFG_REG0 0xa00
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#define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5)
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#define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)
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#define LAN887X_MAC_MODE_RGMII 0x01
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#define LAN887X_MAC_MODE_SGMII 0x03
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#define LAN887X_MIS_DLL_CFG_REG0 0xa01
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#define LAN887X_MIS_DLL_CFG_REG1 0xa02
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#define LAN887X_MIS_DLL_DELAY_EN BIT(15)
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#define LAN887X_MIS_DLL_EN BIT(0)
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#define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\
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LAN887X_MIS_DLL_EN)
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#define LAN887X_MIS_CFG_REG2 0xa03
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#define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2)
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#define LAN887X_MIS_PKT_STAT_REG0 0xa06
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#define LAN887X_MIS_PKT_STAT_REG1 0xa07
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#define LAN887X_MIS_PKT_STAT_REG3 0xa09
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#define LAN887X_MIS_PKT_STAT_REG4 0xa0a
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#define LAN887X_MIS_PKT_STAT_REG5 0xa0b
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#define LAN887X_MIS_PKT_STAT_REG6 0xa0c
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/* Chiptop common registers */
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#define LAN887X_COMMON_LED3_LED2 0xc05
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#define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)
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#define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0
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/* MX chip top registers */
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#define LAN887X_CHIP_SOFT_RST 0xf03f
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#define LAN887X_CHIP_SOFT_RST_RESET BIT(0)
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#define LAN887X_SGMII_CTL 0xf01a
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#define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)
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#define LAN887X_SGMII_PCS_CFG 0xf034
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#define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9)
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#define LAN887X_EFUSE_READ_DAT9 0xf209
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#define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9)
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#define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)
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#define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>"
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#define DRIVER_DESC "Microchip LAN87XX/LAN937x T1 PHY driver"
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#define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver"
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struct access_ereg_val {
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u8 mode;
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@ -105,6 +199,32 @@ struct access_ereg_val {
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u16 mask;
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};
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struct lan887x_hw_stat {
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const char *string;
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u8 mmd;
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u16 reg;
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u8 bits;
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};
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static const struct lan887x_hw_stat lan887x_hw_stats[] = {
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{ "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
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{ "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
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{ "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
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{ "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
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{ "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
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{ "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
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};
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struct lan887x_regwr_map {
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u8 mmd;
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u16 reg;
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u16 val;
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};
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struct lan887x_priv {
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u64 stats[ARRAY_SIZE(lan887x_hw_stats)];
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};
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static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)
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{
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u8 prev_bank;
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@ -860,6 +980,446 @@ static int lan87xx_get_sqi_max(struct phy_device *phydev)
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return LAN87XX_MAX_SQI;
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}
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static int lan887x_rgmii_init(struct phy_device *phydev)
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{
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int ret;
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/* SGMII mux disable */
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ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_SGMII_CTL,
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LAN887X_SGMII_CTL_SGMII_MUX_EN);
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if (ret < 0)
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return ret;
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/* Select MAC_MODE as RGMII */
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
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LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
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LAN887X_MAC_MODE_RGMII);
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if (ret < 0)
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return ret;
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/* Disable PCS */
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ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_SGMII_PCS_CFG,
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LAN887X_SGMII_PCS_CFG_PCS_ENA);
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if (ret < 0)
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return ret;
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/* LAN887x Errata: RGMII rx clock active in SGMII mode
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* Disabled it for SGMII mode
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* Re-enabling it for RGMII mode
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*/
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return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_MIS_CFG_REG0,
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LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
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}
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static int lan887x_sgmii_init(struct phy_device *phydev)
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{
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int ret;
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/* SGMII mux enable */
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ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_SGMII_CTL,
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LAN887X_SGMII_CTL_SGMII_MUX_EN);
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if (ret < 0)
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return ret;
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/* Select MAC_MODE as SGMII */
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
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LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
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LAN887X_MAC_MODE_SGMII);
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if (ret < 0)
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return ret;
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/* LAN887x Errata: RGMII rx clock active in SGMII mode.
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* So disabling it for SGMII mode
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*/
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ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
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LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
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if (ret < 0)
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return ret;
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/* Enable PCS */
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return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
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LAN887X_SGMII_PCS_CFG_PCS_ENA);
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}
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static int lan887x_config_rgmii_en(struct phy_device *phydev)
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{
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int txc;
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int rxc;
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int ret;
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ret = lan887x_rgmii_init(phydev);
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if (ret < 0)
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return ret;
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/* Control bit to enable/disable TX DLL delay line in signal path */
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txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);
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if (txc < 0)
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return txc;
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/* Control bit to enable/disable RX DLL delay line in signal path */
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rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);
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if (rxc < 0)
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return rxc;
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/* Configures the phy to enable RX/TX delay
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* RGMII - TX & RX delays are either added by MAC or not needed,
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* phy should not add
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* RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add
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* RGMII_RX_ID - Configures the PHY to enable the RX delay.
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* The MAC shouldn't add the RX delay
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* RGMII_TX_ID - Configures the PHY to enable the TX delay.
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* The MAC shouldn't add the TX delay in this case
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*/
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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txc &= ~LAN887X_MIS_DLL_CONF;
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rxc &= ~LAN887X_MIS_DLL_CONF;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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txc |= LAN887X_MIS_DLL_CONF;
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rxc |= LAN887X_MIS_DLL_CONF;
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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txc &= ~LAN887X_MIS_DLL_CONF;
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rxc |= LAN887X_MIS_DLL_CONF;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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txc |= LAN887X_MIS_DLL_CONF;
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rxc &= ~LAN887X_MIS_DLL_CONF;
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break;
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default:
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WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface);
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return 0;
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}
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/* Configures the PHY to enable/disable RX delay in signal path */
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
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LAN887X_MIS_DLL_CONF, rxc);
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if (ret < 0)
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return ret;
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/* Configures the PHY to enable/disable the TX delay in signal path */
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return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
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LAN887X_MIS_DLL_CONF, txc);
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}
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static int lan887x_config_phy_interface(struct phy_device *phydev)
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{
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int interface_mode;
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int sgmii_dis;
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int ret;
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/* Read sku efuse data for interfaces supported by sku */
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ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);
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if (ret < 0)
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return ret;
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/* If interface_mode is 1 then efuse sets RGMII operations.
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* If interface mode is 3 then efuse sets SGMII operations.
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*/
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interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE;
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/* SGMII disable is set for RGMII operations */
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sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS;
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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/* Reject RGMII settings for SGMII only sku */
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ret = -EOPNOTSUPP;
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if (!((interface_mode & LAN887X_MAC_MODE_SGMII) ==
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LAN887X_MAC_MODE_SGMII))
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ret = lan887x_config_rgmii_en(phydev);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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/* Reject SGMII setting for RGMII only sku */
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ret = -EOPNOTSUPP;
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if (!sgmii_dis)
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ret = lan887x_sgmii_init(phydev);
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break;
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default:
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/* Reject setting for unsupported interfaces */
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ret = -EOPNOTSUPP;
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}
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return ret;
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}
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static int lan887x_get_features(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_c45_pma_read_abilities(phydev);
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if (ret < 0)
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return ret;
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/* Enable twisted pair */
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linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
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/* First patch only supports 100Mbps and 1000Mbps force-mode.
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* T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later.
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*/
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
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return 0;
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}
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static int lan887x_phy_init(struct phy_device *phydev)
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{
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int ret;
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/* Clear loopback */
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ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_MIS_CFG_REG2,
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LAN887X_MIS_CFG_REG2_FE_LPBK_EN);
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if (ret < 0)
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return ret;
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/* Configure default behavior of led to link and activity for any
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* speed
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*/
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ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
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LAN887X_COMMON_LED3_LED2,
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LAN887X_COMMON_LED2_MODE_SEL_MASK,
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LAN887X_LED_LINK_ACT_ANY_SPEED);
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if (ret < 0)
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return ret;
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/* PHY interface setup */
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return lan887x_config_phy_interface(phydev);
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}
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static int lan887x_phy_config(struct phy_device *phydev,
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const struct lan887x_regwr_map *reg_map, int cnt)
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{
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int ret;
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for (int i = 0; i < cnt; i++) {
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ret = phy_write_mmd(phydev, reg_map[i].mmd,
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reg_map[i].reg, reg_map[i].val);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int lan887x_phy_setup(struct phy_device *phydev)
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{
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static const struct lan887x_regwr_map phy_cfg[] = {
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/* PORT_AFE writes */
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{MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008},
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{MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000},
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{MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040},
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/* 100T1_PCS_VENDOR writes */
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{MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008},
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{MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d},
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/* 100T1 DSP writes */
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{MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
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{MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
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{MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
|
||||
{MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
|
||||
{MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
|
||||
{MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
|
||||
/* 1000T1 DSP writes */
|
||||
{MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
|
||||
{MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
|
||||
{MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
|
||||
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
|
||||
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
|
||||
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
|
||||
{MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
|
||||
{MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
|
||||
{MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
|
||||
/* 1000T1 PCS writes */
|
||||
{MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00},
|
||||
{MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1},
|
||||
};
|
||||
|
||||
return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
|
||||
}
|
||||
|
||||
static int lan887x_100M_setup(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* (Re)configure the speed/mode dependent T1 settings */
|
||||
if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE ||
|
||||
phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){
|
||||
static const struct lan887x_regwr_map phy_cfg[] = {
|
||||
{MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
|
||||
{MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038},
|
||||
{MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
|
||||
};
|
||||
|
||||
ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
|
||||
} else {
|
||||
static const struct lan887x_regwr_map phy_cfg[] = {
|
||||
{MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038},
|
||||
{MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
|
||||
};
|
||||
|
||||
ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
|
||||
}
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
|
||||
LAN887X_REG_REG26_HW_INIT_SEQ_EN);
|
||||
}
|
||||
|
||||
static int lan887x_1000M_setup(struct phy_device *phydev)
|
||||
{
|
||||
static const struct lan887x_regwr_map phy_cfg[] = {
|
||||
{MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f},
|
||||
{MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
|
||||
};
|
||||
int ret;
|
||||
|
||||
/* (Re)configure the speed/mode dependent T1 settings */
|
||||
ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
|
||||
LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
|
||||
}
|
||||
|
||||
static int lan887x_link_setup(struct phy_device *phydev)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (phydev->speed == SPEED_1000)
|
||||
ret = lan887x_1000M_setup(phydev);
|
||||
else if (phydev->speed == SPEED_100)
|
||||
ret = lan887x_100M_setup(phydev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* LAN887x Errata: speed configuration changes require soft reset
|
||||
* and chip soft reset
|
||||
*/
|
||||
static int lan887x_phy_reset(struct phy_device *phydev)
|
||||
{
|
||||
int ret, val;
|
||||
|
||||
/* Clear 1000M link sync */
|
||||
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
|
||||
LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Clear 100M link sync */
|
||||
ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
|
||||
LAN887X_REG_REG26_HW_INIT_SEQ_EN);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Chiptop soft-reset to allow the speed/mode change */
|
||||
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,
|
||||
LAN887X_CHIP_SOFT_RST_RESET);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* CL22 soft-reset to let the link re-train */
|
||||
ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Wait for reset complete or timeout if > 10ms */
|
||||
return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
|
||||
5000, 10000, true);
|
||||
}
|
||||
|
||||
static int lan887x_phy_reconfig(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
linkmode_zero(phydev->advertising);
|
||||
|
||||
ret = genphy_c45_pma_setup_forced(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return lan887x_link_setup(phydev);
|
||||
}
|
||||
|
||||
static int lan887x_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* LAN887x Errata: speed configuration changes require soft reset
|
||||
* and chip soft reset
|
||||
*/
|
||||
ret = lan887x_phy_reset(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return lan887x_phy_reconfig(phydev);
|
||||
}
|
||||
|
||||
static int lan887x_probe(struct phy_device *phydev)
|
||||
{
|
||||
struct lan887x_priv *priv;
|
||||
|
||||
priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
phydev->priv = priv;
|
||||
|
||||
return lan887x_phy_setup(phydev);
|
||||
}
|
||||
|
||||
static u64 lan887x_get_stat(struct phy_device *phydev, int i)
|
||||
{
|
||||
struct lan887x_hw_stat stat = lan887x_hw_stats[i];
|
||||
struct lan887x_priv *priv = phydev->priv;
|
||||
int val;
|
||||
u64 ret;
|
||||
|
||||
if (stat.mmd)
|
||||
val = phy_read_mmd(phydev, stat.mmd, stat.reg);
|
||||
else
|
||||
val = phy_read(phydev, stat.reg);
|
||||
|
||||
if (val < 0) {
|
||||
ret = U64_MAX;
|
||||
} else {
|
||||
val = val & ((1 << stat.bits) - 1);
|
||||
priv->stats[i] += val;
|
||||
ret = priv->stats[i];
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void lan887x_get_stats(struct phy_device *phydev,
|
||||
struct ethtool_stats *stats, u64 *data)
|
||||
{
|
||||
for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
|
||||
data[i] = lan887x_get_stat(phydev, i);
|
||||
}
|
||||
|
||||
static int lan887x_get_sset_count(struct phy_device *phydev)
|
||||
{
|
||||
return ARRAY_SIZE(lan887x_hw_stats);
|
||||
}
|
||||
|
||||
static void lan887x_get_strings(struct phy_device *phydev, u8 *data)
|
||||
{
|
||||
for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
|
||||
ethtool_puts(&data, lan887x_hw_stats[i].string);
|
||||
}
|
||||
|
||||
static struct phy_driver microchip_t1_phy_driver[] = {
|
||||
{
|
||||
PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX),
|
||||
@ -894,6 +1454,20 @@ static struct phy_driver microchip_t1_phy_driver[] = {
|
||||
.get_sqi_max = lan87xx_get_sqi_max,
|
||||
.cable_test_start = lan87xx_cable_test_start,
|
||||
.cable_test_get_status = lan87xx_cable_test_get_status,
|
||||
},
|
||||
{
|
||||
PHY_ID_MATCH_MODEL(PHY_ID_LAN887X),
|
||||
.name = "Microchip LAN887x T1 PHY",
|
||||
.probe = lan887x_probe,
|
||||
.get_features = lan887x_get_features,
|
||||
.config_init = lan887x_phy_init,
|
||||
.config_aneg = lan887x_config_aneg,
|
||||
.get_stats = lan887x_get_stats,
|
||||
.get_sset_count = lan887x_get_sset_count,
|
||||
.get_strings = lan887x_get_strings,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_status = genphy_c45_read_status,
|
||||
}
|
||||
};
|
||||
|
||||
@ -902,6 +1476,7 @@ module_phy_driver(microchip_t1_phy_driver);
|
||||
static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
|
||||
{ PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user