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[Blackfin] arch: fix gdb testing regression
When transferring to IRQ5 from an exception, save SYSCFG in memory across the transfer and clear the trace bit. When we get a single step exception, check whether we can safely clear the trace bit in SYSCFG. We can (and should) clear it after the first instruction of the interrupt handler; the first insn saves SYSCFG to the stack in all handlers. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Bernd Schmidt
Bryan Wu
parent
8513c42edb
commit
0893f1250f
@ -151,26 +151,62 @@ ENTRY(_ex_soft_bp)
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ENDPROC(_ex_soft_bp)
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ENTRY(_ex_single_step)
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/* If we just returned from an interrupt, the single step event is
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for the RTI instruction. */
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r7 = retx;
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r6 = reti;
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cc = r7 == r6;
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if cc jump _bfin_return_from_exception
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if cc jump _bfin_return_from_exception;
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/* If we were in user mode, do the single step normally. */
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p5.l = lo(IPEND);
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p5.h = hi(IPEND);
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r6 = [p5];
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r7 = 0xffe0 (z);
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r7 = r7 & r6;
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cc = r7 == 0;
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if !cc jump 1f;
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/* Single stepping only a single instruction, so clear the trace
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* bit here. */
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r7 = syscfg;
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bitclr (r7, 0);
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syscfg = R7;
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jump _ex_trap_c;
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1:
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/*
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* We were in an interrupt handler. By convention, all of them save
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* SYSCFG with their first instruction, so by checking whether our
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* RETX points at the entry point, we can determine whether to allow
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* a single step, or whether to clear SYSCFG.
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*
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* First, find out the interrupt level and the event vector for it.
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*/
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p5.l = lo(EVT0);
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p5.h = hi(EVT0);
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p5 += -4;
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2:
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r7 = rot r7 by -1;
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p5 += 4;
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if !cc jump 2b;
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/* What we actually do is test for the _second_ instruction in the
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* IRQ handler. That way, if there are insns following the restore
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* of SYSCFG after leaving the handler, we will not turn off SYSCFG
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* for them. */
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r7 = [p5];
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r7 += 2;
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r6 = RETX;
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cc = R7 == R6;
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if !cc jump _bfin_return_from_exception;
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r7 = syscfg;
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bitclr (r7, 0);
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syscfg = R7;
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p5.l = lo(IPEND);
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p5.h = hi(IPEND);
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r6 = [p5];
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cc = bittst(r6, 5);
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if !cc jump _ex_trap_c;
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p4.l = lo(EVT5);
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p4.h = hi(EVT5);
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r6.h = _exception_to_level5;
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r6.l = _exception_to_level5;
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r7 = [p4];
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cc = r6 == r7;
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if !cc jump _ex_trap_c;
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/* Fall through to _bfin_return_from_exception. */
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ENDPROC(_ex_single_step)
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ENTRY(_bfin_return_from_exception)
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@ -234,20 +270,26 @@ ENTRY(_ex_trap_c)
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p5.l = _saved_icplb_fault_addr;
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[p5] = r7;
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p4.l = __retx;
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p4.h = __retx;
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p4.l = _excpt_saved_stuff;
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p4.h = _excpt_saved_stuff;
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r6 = retx;
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[p4] = r6;
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p4.l = lo(SAFE_USER_INSTRUCTION);
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p4.h = hi(SAFE_USER_INSTRUCTION);
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retx = p4;
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r6 = SYSCFG;
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[p4 + 4] = r6;
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BITCLR(r6, 0);
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SYSCFG = r6;
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/* Disable all interrupts, but make sure level 5 is enabled so
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* we can switch to that level. Save the old mask. */
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cli r6;
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p4.l = _excpt_saved_imask;
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p4.h = _excpt_saved_imask;
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[p4] = r6;
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[p4 + 8] = r6;
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p4.l = lo(SAFE_USER_INSTRUCTION);
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p4.h = hi(SAFE_USER_INSTRUCTION);
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retx = p4;
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r6 = 0x3f;
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sti r6;
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@ -312,16 +354,17 @@ ENDPROC(_double_fault)
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ENTRY(_exception_to_level5)
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SAVE_ALL_SYS
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p4.l = __retx;
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p4.h = __retx;
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p4.l = _excpt_saved_stuff;
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p4.h = _excpt_saved_stuff;
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r6 = [p4];
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[sp + PT_PC] = r6;
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r6 = [p4 + 4];
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[sp + PT_SYSCFG] = r6;
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/* Restore interrupt mask. We haven't pushed RETI, so this
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* doesn't enable interrupts until we return from this handler. */
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p4.l = _excpt_saved_imask;
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p4.h = _excpt_saved_imask;
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r6 = [p4];
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r6 = [p4 + 8];
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sti r6;
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/* Restore the hardware error vector. */
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@ -1349,7 +1392,14 @@ ENTRY(_sys_call_table)
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.rept NR_syscalls-(.-_sys_call_table)/4
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.long _sys_ni_syscall
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.endr
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_excpt_saved_imask:
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/*
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* Used to save the real RETX, IMASK and SYSCFG when temporarily
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* storing safe values across the transition from exception to IRQ5.
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*/
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_excpt_saved_stuff:
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.long 0;
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.long 0;
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.long 0;
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_exception_stack:
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@ -1363,7 +1413,3 @@ _exception_stack_top:
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_last_cplb_fault_retx:
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.long 0;
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#endif
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/* Used to save the real RETX when temporarily storing a safe
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* return address. */
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__retx:
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.long 0;
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@ -17,6 +17,11 @@
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#define PF_DTRACE_OFF 1
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#define PF_DTRACE_BIT 5
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/*
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* NOTE! The single-stepping code assumes that all interrupt handlers
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* start by saving SYSCFG on the stack with their first instruction.
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*/
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/* This one is used for exceptions, emulation, and NMI. It doesn't push
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RETI and doesn't do cli. */
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#define SAVE_ALL_SYS save_context_no_interrupts
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@ -27,6 +27,11 @@
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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* NOTE! The single-stepping code assumes that all interrupt handlers
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* start by saving SYSCFG on the stack with their first instruction.
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*/
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/*
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* Code to save processor context.
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* We even save the register which are preserved by a function call
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