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ARM: mmp: remove all board files

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The old-style board files were marked as 'unused' a while ago
and can now be removed for good, leaving only devicetree based
boot support.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-09-29 15:39:20 +02:00
parent 90ca4d9015
commit 06f11dfb5b
16 changed files with 0 additions and 2566 deletions
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3
arch/arm/configs/pxa168_defconfig
View File

@ -1,9 +1,6 @@
CONFIG_SYSVIPC=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_MACH_ASPENITE=y
CONFIG_MACH_ZYLONITE2=y
CONFIG_MACH_AVENGERS_LITE=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y

2
arch/arm/configs/pxa910_defconfig
View File

@ -11,8 +11,6 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_MACH_TAVOREVB=y
CONFIG_MACH_TTC_DKB=y
CONFIG_AEABI=y
CONFIG_FPE_NWFPE=y
CONFIG_SLAB=y

96
arch/arm/mach-mmp/Kconfig
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@ -13,99 +13,6 @@ if ARCH_MMP
menu "Marvell PXA168/910/MMP2 Implementations"
if ATAGS
config MACH_ASPENITE
bool "Marvell's PXA168 Aspenite Development Board"
depends on ARCH_MULTI_V5
depends on UNUSED_BOARD_FILES
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Aspenite Development Board.
config MACH_ZYLONITE2
bool "Marvell's PXA168 Zylonite2 Development Board"
depends on ARCH_MULTI_V5
depends on UNUSED_BOARD_FILES
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Zylonite2 Development Board.
config MACH_AVENGERS_LITE
bool "Marvell's PXA168 Avengers Lite Development Board"
depends on ARCH_MULTI_V5
depends on UNUSED_BOARD_FILES
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Avengers Lite Development Board.
config MACH_TTC_DKB
bool "Marvell's PXA910 TavorEVB/TTC_DKB Development Board"
depends on ARCH_MULTI_V5
depends on UNUSED_BOARD_FILES
select CPU_PXA910
help
Say 'Y' here if you want to support the Marvell PXA910-based
TTC_DKB Development Board.
config MACH_BROWNSTONE
bool "Marvell's Brownstone Development Platform"
depends on ARCH_MULTI_V7
depends on UNUSED_BOARD_FILES
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-based
Brown Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv7 architecture.
config MACH_FLINT
bool "Marvell's Flint Development Platform"
depends on ARCH_MULTI_V7
depends on UNUSED_BOARD_FILES
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-based
Flint Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv7 architecture.
config MACH_MARVELL_JASPER
bool "Marvell's Jasper Development Platform"
depends on ARCH_MULTI_V7
depends on UNUSED_BOARD_FILES
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-base
Jasper Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv7 architecture.
config MACH_TETON_BGA
bool "Marvell's PXA168 Teton BGA Development Board"
depends on ARCH_MULTI_V5
depends on UNUSED_BOARD_FILES
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Teton BGA Development Board.
config MACH_GPLUGD
bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
depends on ARCH_MULTI_V5
depends on UNUSED_BOARD_FILES
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
GuruPlug Display (gplugD) Board
endif
config MACH_MMP_DT
bool "Support MMP (ARMv5) platforms from device tree"
depends on ARCH_MULTI_V5
@ -178,7 +85,4 @@ config USB_EHCI_MV_U2O
help
Enables support for OTG controller which can be switched to host mode.
config MMP_SRAM
bool
endif

9
arch/arm/mach-mmp/Makefile
View File

@ -19,15 +19,6 @@ obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o
endif
# board support
obj-$(CONFIG_MACH_ASPENITE) += aspenite.o
obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o
obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o
obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
obj-$(CONFIG_MACH_GPLUGD) += gplugd.o

284
arch/arm/mach-mmp/aspenite.c
View File

@ -1,284 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/aspenite.c
*
* Support for the Marvell PXA168-based Aspenite and Zylonite2
* Development Platform.
*/
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/rawnand.h>
#include <linux/interrupt.h>
#include <linux/platform_data/mv_usb.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <video/pxa168fb.h>
#include <linux/input.h>
#include <linux/platform_data/keypad-pxa27x.h>
#include "addr-map.h"
#include "mfp-pxa168.h"
#include "pxa168.h"
#include "pxa910.h"
#include "irqs.h"
#include "common.h"
static unsigned long common_pin_config[] __initdata = {
/* Data Flash Interface */
GPIO0_DFI_D15,
GPIO1_DFI_D14,
GPIO2_DFI_D13,
GPIO3_DFI_D12,
GPIO4_DFI_D11,
GPIO5_DFI_D10,
GPIO6_DFI_D9,
GPIO7_DFI_D8,
GPIO8_DFI_D7,
GPIO9_DFI_D6,
GPIO10_DFI_D5,
GPIO11_DFI_D4,
GPIO12_DFI_D3,
GPIO13_DFI_D2,
GPIO14_DFI_D1,
GPIO15_DFI_D0,
/* Static Memory Controller */
GPIO18_SMC_nCS0,
GPIO34_SMC_nCS1,
GPIO23_SMC_nLUA,
GPIO25_SMC_nLLA,
GPIO28_SMC_RDY,
GPIO29_SMC_SCLK,
GPIO35_SMC_BE1,
GPIO36_SMC_BE2,
GPIO27_GPIO, /* Ethernet IRQ */
/* UART1 */
GPIO107_UART1_RXD,
GPIO108_UART1_TXD,
/* SSP1 */
GPIO113_I2S_MCLK,
GPIO114_I2S_FRM,
GPIO115_I2S_BCLK,
GPIO116_I2S_RXD,
GPIO117_I2S_TXD,
/* LCD */
GPIO56_LCD_FCLK_RD,
GPIO57_LCD_LCLK_A0,
GPIO58_LCD_PCLK_WR,
GPIO59_LCD_DENA_BIAS,
GPIO60_LCD_DD0,
GPIO61_LCD_DD1,
GPIO62_LCD_DD2,
GPIO63_LCD_DD3,
GPIO64_LCD_DD4,
GPIO65_LCD_DD5,
GPIO66_LCD_DD6,
GPIO67_LCD_DD7,
GPIO68_LCD_DD8,
GPIO69_LCD_DD9,
GPIO70_LCD_DD10,
GPIO71_LCD_DD11,
GPIO72_LCD_DD12,
GPIO73_LCD_DD13,
GPIO74_LCD_DD14,
GPIO75_LCD_DD15,
GPIO76_LCD_DD16,
GPIO77_LCD_DD17,
GPIO78_LCD_DD18,
GPIO79_LCD_DD19,
GPIO80_LCD_DD20,
GPIO81_LCD_DD21,
GPIO82_LCD_DD22,
GPIO83_LCD_DD23,
/* Keypad */
GPIO109_KP_MKIN1,
GPIO110_KP_MKIN0,
GPIO111_KP_MKOUT7,
GPIO112_KP_MKOUT6,
GPIO121_KP_MKIN4,
};
static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = SMC_CS1_PHYS_BASE + 0x300,
.end = SMC_CS1_PHYS_BASE + 0xfffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MMP_GPIO_TO_IRQ(27),
.end = MMP_GPIO_TO_IRQ(27),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct mtd_partition aspenite_nand_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = SZ_1M,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_8M,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = (SZ_2M + SZ_1M),
.mask_flags = 0,
}, {
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = SZ_32M + SZ_16M,
.mask_flags = 0,
}
};
static struct pxa3xx_nand_platform_data aspenite_nand_info = {
.parts = aspenite_nand_partitions,
.nr_parts = ARRAY_SIZE(aspenite_nand_partitions),
};
static struct i2c_board_info aspenite_i2c_info[] __initdata = {
{ I2C_BOARD_INFO("wm8753", 0x1b), },
};
static struct fb_videomode video_modes[] = {
[0] = {
.pixclock = 30120,
.refresh = 60,
.xres = 800,
.yres = 480,
.hsync_len = 1,
.left_margin = 215,
.right_margin = 40,
.vsync_len = 1,
.upper_margin = 34,
.lower_margin = 10,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
},
};
struct pxa168fb_mach_info aspenite_lcd_info = {
.id = "Graphic Frame",
.modes = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
.pix_fmt = PIX_FMT_RGB565,
.io_pin_allocation_mode = PIN_MODE_DUMB_24,
.dumb_mode = DUMB_MODE_RGB888,
.active = 1,
.panel_rbswap = 0,
.invert_pixclock = 0,
};
static const unsigned int aspenite_matrix_key_map[] = {
KEY(0, 6, KEY_UP), /* SW 4 */
KEY(0, 7, KEY_DOWN), /* SW 5 */
KEY(1, 6, KEY_LEFT), /* SW 6 */
KEY(1, 7, KEY_RIGHT), /* SW 7 */
KEY(4, 6, KEY_ENTER), /* SW 8 */
KEY(4, 7, KEY_ESC), /* SW 9 */
};
static struct matrix_keymap_data aspenite_matrix_keymap_data = {
.keymap = aspenite_matrix_key_map,
.keymap_size = ARRAY_SIZE(aspenite_matrix_key_map),
};
static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
.matrix_key_rows = 5,
.matrix_key_cols = 8,
.matrix_keymap_data = &aspenite_matrix_keymap_data,
.debounce_interval = 30,
};
#if IS_ENABLED(CONFIG_USB_EHCI_MV)
static struct mv_usb_platform_data pxa168_sph_pdata = {
.mode = MV_USB_MODE_HOST,
.phy_init = pxa_usb_phy_init,
.phy_deinit = pxa_usb_phy_deinit,
.set_vbus = NULL,
};
#endif
static void __init common_init(void)
{
mfp_config(ARRAY_AND_SIZE(common_pin_config));
/* on-chip devices */
pxa168_add_uart(1);
pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
pxa168_add_ssp(1);
pxa168_add_nand(&aspenite_nand_info);
pxa168_add_fb(&aspenite_lcd_info);
pxa168_add_keypad(&aspenite_keypad_info);
platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&pxa168_device_gpio);
/* off-chip devices */
platform_device_register(&smc91x_device);
#if IS_ENABLED(CONFIG_USB_SUPPORT)
#if IS_ENABLED(CONFIG_PHY_PXA_USB)
platform_device_register(&pxa168_device_usb_phy);
#endif
#if IS_ENABLED(CONFIG_USB_EHCI_MV)
pxa168_add_usb_host(&pxa168_sph_pdata);
#endif
#endif
}
MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
.map_io = mmp_map_io,
.nr_irqs = MMP_NR_IRQS,
.init_irq = pxa168_init_irq,
.init_time = pxa168_timer_init,
.init_machine = common_init,
.restart = pxa168_restart,
MACHINE_END
MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
.map_io = mmp_map_io,
.nr_irqs = MMP_NR_IRQS,
.init_irq = pxa168_init_irq,
.init_time = pxa168_timer_init,
.init_machine = common_init,
.restart = pxa168_restart,
MACHINE_END

55
arch/arm/mach-mmp/avengers_lite.c
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@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/avengers_lite.c
*
* Support for the Marvell PXA168-based Avengers lite Development Platform.
*
* Copyright (C) 2009-2010 Marvell International Ltd.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio-pxa.h>
#include <linux/platform_device.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "addr-map.h"
#include "mfp-pxa168.h"
#include "pxa168.h"
#include "irqs.h"
#include "common.h"
#include <linux/delay.h>
/* Avengers lite MFP configurations */
static unsigned long avengers_lite_pin_config_V16F[] __initdata = {
/* DEBUG_UART */
GPIO88_UART2_TXD,
GPIO89_UART2_RXD,
};
static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static void __init avengers_lite_init(void)
{
mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));
/* on-chip devices */
pxa168_add_uart(2);
platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&pxa168_device_gpio);
}
MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
.map_io = mmp_map_io,
.nr_irqs = MMP_NR_IRQS,
.init_irq = pxa168_init_irq,
.init_time = pxa168_timer_init,
.init_machine = avengers_lite_init,
.restart = pxa168_restart,
MACHINE_END

237
arch/arm/mach-mmp/brownstone.c
View File

@ -1,237 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/brownstone.c
*
* Support for the Marvell Brownstone Development Platform.
*
* Copyright (C) 2009-2010 Marvell International Ltd.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio-pxa.h>
#include <linux/gpio/machine.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/max8649.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/max8925.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "addr-map.h"
#include "mfp-mmp2.h"
#include "mmp2.h"
#include "irqs.h"
#include "common.h"
#define BROWNSTONE_NR_IRQS (MMP_NR_IRQS + 40)
#define GPIO_5V_ENABLE (89)
static unsigned long brownstone_pin_config[] __initdata = {
/* UART1 */
GPIO29_UART1_RXD,
GPIO30_UART1_TXD,
/* UART3 */
GPIO51_UART3_RXD,
GPIO52_UART3_TXD,
/* DFI */
GPIO168_DFI_D0,
GPIO167_DFI_D1,
GPIO166_DFI_D2,
GPIO165_DFI_D3,
GPIO107_DFI_D4,
GPIO106_DFI_D5,
GPIO105_DFI_D6,
GPIO104_DFI_D7,
GPIO111_DFI_D8,
GPIO164_DFI_D9,
GPIO163_DFI_D10,
GPIO162_DFI_D11,
GPIO161_DFI_D12,
GPIO110_DFI_D13,
GPIO109_DFI_D14,
GPIO108_DFI_D15,
GPIO143_ND_nCS0,
GPIO144_ND_nCS1,
GPIO147_ND_nWE,
GPIO148_ND_nRE,
GPIO150_ND_ALE,
GPIO149_ND_CLE,
GPIO112_ND_RDY0,
GPIO160_ND_RDY1,
/* PMIC */
PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
/* MMC0 */
GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
GPIO136_MMC1_CMD | MFP_PULL_HIGH,
GPIO139_MMC1_CLK,
GPIO140_MMC1_CD | MFP_PULL_LOW,
GPIO141_MMC1_WP | MFP_PULL_LOW,
/* MMC1 */
GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
GPIO41_MMC2_CMD | MFP_PULL_HIGH,
GPIO42_MMC2_CLK,
/* MMC2 */
GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
GPIO112_MMC3_CMD | MFP_PULL_HIGH,
GPIO151_MMC3_CLK,
/* 5V regulator */
GPIO89_GPIO,
};
static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static struct regulator_consumer_supply max8649_supply[] = {
REGULATOR_SUPPLY("vcc_core", NULL),
};
static struct regulator_init_data max8649_init_data = {
.constraints = {
.name = "vcc_core range",
.min_uV = 1150000,
.max_uV = 1280000,
.always_on = 1,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = 1,
.consumer_supplies = &max8649_supply[0],
};
static struct max8649_platform_data brownstone_max8649_info = {
.mode = 2, /* VID1 = 1, VID0 = 0 */
.extclk = 0,
.ramp_timing = MAX8649_RAMP_32MV,
.regulator = &max8649_init_data,
};
static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
REGULATOR_SUPPLY("v_5vp", NULL),
};
static struct regulator_init_data brownstone_v_5vp_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies),
.consumer_supplies = brownstone_v_5vp_supplies,
};
static struct fixed_voltage_config brownstone_v_5vp = {
.supply_name = "v_5vp",
.microvolts = 5000000,
.enabled_at_boot = 1,
.init_data = &brownstone_v_5vp_data,
};
static struct platform_device brownstone_v_5vp_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &brownstone_v_5vp,
},
};
static struct gpiod_lookup_table brownstone_v_5vp_gpiod_table = {
.dev_id = "reg-fixed-voltage.1", /* .id set to 1 above */
.table = {
GPIO_LOOKUP("gpio-pxa", GPIO_5V_ENABLE,
NULL, GPIO_ACTIVE_HIGH),
{ },
},
};
static struct max8925_platform_data brownstone_max8925_info = {
.irq_base = MMP_NR_IRQS,
};
static struct i2c_board_info brownstone_twsi1_info[] = {
[0] = {
.type = "max8649",
.addr = 0x60,
.platform_data = &brownstone_max8649_info,
},
[1] = {
.type = "max8925",
.addr = 0x3c,
.irq = IRQ_MMP2_PMIC,
.platform_data = &brownstone_max8925_info,
},
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
.clk_delay_cycles = 0x1f,
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = {
.clk_delay_cycles = 0x1f,
.flags = PXA_FLAG_CARD_PERMANENT
| PXA_FLAG_SD_8_BIT_CAPABLE_SLOT,
};
static struct sram_platdata mmp2_asram_platdata = {
.pool_name = "asram",
.granularity = SRAM_GRANULARITY,
};
static struct sram_platdata mmp2_isram_platdata = {
.pool_name = "isram",
.granularity = SRAM_GRANULARITY,
};
static void __init brownstone_init(void)
{
mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
/* on-chip devices */
mmp2_add_uart(1);
mmp2_add_uart(3);
platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&mmp2_device_gpio);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
mmp2_add_asram(&mmp2_asram_platdata);
mmp2_add_isram(&mmp2_isram_platdata);
/* enable 5v regulator */
gpiod_add_lookup_table(&brownstone_v_5vp_gpiod_table);
platform_device_register(&brownstone_v_5vp_device);
}
MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
/* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
.map_io = mmp_map_io,
.nr_irqs = BROWNSTONE_NR_IRQS,
.init_irq = mmp2_init_irq,
.init_time = mmp2_timer_init,
.init_machine = brownstone_init,
.restart = mmp_restart,
MACHINE_END

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arch/arm/mach-mmp/flint.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/flint.c
*
* Support for the Marvell Flint Development Platform.
*
* Copyright (C) 2009 Marvell International Ltd.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/smc91x.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "addr-map.h"
#include "mfp-mmp2.h"
#include "mmp2.h"
#include "irqs.h"
#include "common.h"
#define FLINT_NR_IRQS (MMP_NR_IRQS + 48)
static unsigned long flint_pin_config[] __initdata = {
/* UART1 */
GPIO45_UART1_RXD,
GPIO46_UART1_TXD,
/* UART2 */
GPIO47_UART2_RXD,
GPIO48_UART2_TXD,
/* SMC */
GPIO151_SMC_SCLK,
GPIO145_SMC_nCS0,
GPIO146_SMC_nCS1,
GPIO152_SMC_BE0,
GPIO153_SMC_BE1,
GPIO154_SMC_IRQ,
GPIO113_SMC_RDY,
/*Ethernet*/
GPIO155_GPIO,
/* DFI */
GPIO168_DFI_D0,
GPIO167_DFI_D1,
GPIO166_DFI_D2,
GPIO165_DFI_D3,
GPIO107_DFI_D4,
GPIO106_DFI_D5,
GPIO105_DFI_D6,
GPIO104_DFI_D7,
GPIO111_DFI_D8,
GPIO164_DFI_D9,
GPIO163_DFI_D10,
GPIO162_DFI_D11,
GPIO161_DFI_D12,
GPIO110_DFI_D13,
GPIO109_DFI_D14,
GPIO108_DFI_D15,
GPIO143_ND_nCS0,
GPIO144_ND_nCS1,
GPIO147_ND_nWE,
GPIO148_ND_nRE,
GPIO150_ND_ALE,
GPIO149_ND_CLE,
GPIO112_ND_RDY0,
GPIO160_ND_RDY1,
};
static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static struct smc91x_platdata flint_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = SMC_CS1_PHYS_BASE + 0x300,
.end = SMC_CS1_PHYS_BASE + 0xfffff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MMP_GPIO_TO_IRQ(155),
.end = MMP_GPIO_TO_IRQ(155),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
}
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &flint_smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static void __init flint_init(void)
{
mfp_config(ARRAY_AND_SIZE(flint_pin_config));
/* on-chip devices */
mmp2_add_uart(1);
mmp2_add_uart(2);
platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&mmp2_device_gpio);
/* off-chip devices */
platform_device_register(&smc91x_device);
}
MACHINE_START(FLINT, "Flint Development Platform")
.map_io = mmp_map_io,
.nr_irqs = FLINT_NR_IRQS,
.init_irq = mmp2_init_irq,
.init_time = mmp2_timer_init,
.init_machine = flint_init,
.restart = mmp_restart,
MACHINE_END

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arch/arm/mach-mmp/gplugd.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/gplugd.c
*
* Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include "irqs.h"
#include "pxa168.h"
#include "mfp-pxa168.h"
#include "common.h"
static unsigned long gplugd_pin_config[] __initdata = {
/* UART3 */
GPIO8_UART3_TXD,
GPIO9_UART3_RXD,
GPIO1O_UART3_CTS,
GPIO11_UART3_RTS,
/* USB OTG PEN */
GPIO18_GPIO,
/* MMC2 */
GPIO28_MMC2_CMD,
GPIO29_MMC2_CLK,
GPIO30_MMC2_DAT0,
GPIO31_MMC2_DAT1,
GPIO32_MMC2_DAT2,
GPIO33_MMC2_DAT3,
/* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */
GPIO35_GPIO,
GPIO36_GPIO, /* CEC Interrupt */
/* MMC1 */
GPIO43_MMC1_CLK,
GPIO49_MMC1_CMD,
GPIO41_MMC1_DAT0,
GPIO40_MMC1_DAT1,
GPIO52_MMC1_DAT2,
GPIO51_MMC1_DAT3,
GPIO53_MMC1_CD,
/* LCD */
GPIO56_LCD_FCLK_RD,
GPIO57_LCD_LCLK_A0,
GPIO58_LCD_PCLK_WR,
GPIO59_LCD_DENA_BIAS,
GPIO60_LCD_DD0,
GPIO61_LCD_DD1,
GPIO62_LCD_DD2,
GPIO63_LCD_DD3,
GPIO64_LCD_DD4,
GPIO65_LCD_DD5,
GPIO66_LCD_DD6,
GPIO67_LCD_DD7,
GPIO68_LCD_DD8,
GPIO69_LCD_DD9,
GPIO70_LCD_DD10,
GPIO71_LCD_DD11,
GPIO72_LCD_DD12,
GPIO73_LCD_DD13,
GPIO74_LCD_DD14,
GPIO75_LCD_DD15,
GPIO76_LCD_DD16,
GPIO77_LCD_DD17,
GPIO78_LCD_DD18,
GPIO79_LCD_DD19,
GPIO80_LCD_DD20,
GPIO81_LCD_DD21,
GPIO82_LCD_DD22,
GPIO83_LCD_DD23,
/* GPIO */
GPIO84_GPIO,
GPIO85_GPIO,
/* Fast-Ethernet*/
GPIO86_TX_CLK,
GPIO87_TX_EN,
GPIO88_TX_DQ3,
GPIO89_TX_DQ2,
GPIO90_TX_DQ1,
GPIO91_TX_DQ0,
GPIO92_MII_CRS,
GPIO93_MII_COL,
GPIO94_RX_CLK,
GPIO95_RX_ER,
GPIO96_RX_DQ3,
GPIO97_RX_DQ2,
GPIO98_RX_DQ1,
GPIO99_RX_DQ0,
GPIO100_MII_MDC,
GPIO101_MII_MDIO,
GPIO103_RX_DV,
GPIO104_GPIO, /* Reset PHY */
/* RTC interrupt */
GPIO102_GPIO,
/* I2C */
GPIO105_CI2C_SDA,
GPIO106_CI2C_SCL,
/* SPI NOR Flash on SSP2 */
GPIO107_SSP2_RXD,
GPIO108_SSP2_TXD,
GPIO110_GPIO, /* SPI_CSn */
GPIO111_SSP2_CLK,
/* Select JTAG */
GPIO109_GPIO,
/* I2S */
GPIO114_I2S_FRM,
GPIO115_I2S_BCLK,
GPIO116_I2S_TXD
};
static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static struct i2c_board_info gplugd_i2c_board_info[] = {
{
.type = "isl1208",
.addr = 0x6F,
}
};
/* Bring PHY out of reset by setting GPIO 104 */
static int gplugd_eth_init(void)
{
if (unlikely(gpio_request(104, "ETH_RESET_N"))) {
printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet "
"PHY out of reset\n");
return -EIO;
}
gpio_direction_output(104, 1);
gpio_free(104);
return 0;
}
struct pxa168_eth_platform_data gplugd_eth_platform_data = {
.port_number = 0,
.phy_addr = 0,
.speed = 0, /* Autonagotiation */
.intf = PHY_INTERFACE_MODE_RMII,
.init = gplugd_eth_init,
};
static void __init select_disp_freq(void)
{
/* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) {
printk(KERN_ERR "Can't get hold of GPIO 35 to select display "
"frequency\n");
} else {
gpio_direction_output(35, 1);
gpio_free(35);
}
if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
printk(KERN_ERR "Can't get hold of GPIO 85 to select display "
"frequency\n");
} else {
gpio_direction_output(85, 0);
gpio_free(85);
}
}
static void __init gplugd_init(void)
{
mfp_config(ARRAY_AND_SIZE(gplugd_pin_config));
select_disp_freq();
/* on-chip devices */
pxa168_add_uart(3);
pxa168_add_ssp(1);
pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&pxa168_device_gpio);
pxa168_add_eth(&gplugd_eth_platform_data);
}
MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
.map_io = mmp_map_io,
.nr_irqs = MMP_NR_IRQS,
.init_irq = pxa168_init_irq,
.init_time = pxa168_timer_init,
.init_machine = gplugd_init,
.restart = pxa168_restart,
MACHINE_END

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arch/arm/mach-mmp/jasper.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/jasper.c
*
* Support for the Marvell Jasper Development Platform.
*
* Copyright (C) 2009-2010 Marvell International Ltd.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio-pxa.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/max8649.h>
#include <linux/mfd/max8925.h>
#include <linux/interrupt.h>
#include "irqs.h"
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "addr-map.h"
#include "mfp-mmp2.h"
#include "mmp2.h"
#include "common.h"
#define JASPER_NR_IRQS (MMP_NR_IRQS + 48)
static unsigned long jasper_pin_config[] __initdata = {
/* UART1 */
GPIO29_UART1_RXD,
GPIO30_UART1_TXD,
/* UART3 */
GPIO51_UART3_RXD,
GPIO52_UART3_TXD,
/* DFI */
GPIO168_DFI_D0,
GPIO167_DFI_D1,
GPIO166_DFI_D2,
GPIO165_DFI_D3,
GPIO107_DFI_D4,
GPIO106_DFI_D5,
GPIO105_DFI_D6,
GPIO104_DFI_D7,
GPIO111_DFI_D8,
GPIO164_DFI_D9,
GPIO163_DFI_D10,
GPIO162_DFI_D11,
GPIO161_DFI_D12,
GPIO110_DFI_D13,
GPIO109_DFI_D14,
GPIO108_DFI_D15,
GPIO143_ND_nCS0,
GPIO144_ND_nCS1,
GPIO147_ND_nWE,
GPIO148_ND_nRE,
GPIO150_ND_ALE,
GPIO149_ND_CLE,
GPIO112_ND_RDY0,
GPIO160_ND_RDY1,
/* PMIC */
PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
/* MMC1 */
GPIO131_MMC1_DAT3,
GPIO132_MMC1_DAT2,
GPIO133_MMC1_DAT1,
GPIO134_MMC1_DAT0,
GPIO136_MMC1_CMD,
GPIO139_MMC1_CLK,
GPIO140_MMC1_CD,
GPIO141_MMC1_WP,
/* MMC2 */
GPIO37_MMC2_DAT3,
GPIO38_MMC2_DAT2,
GPIO39_MMC2_DAT1,
GPIO40_MMC2_DAT0,
GPIO41_MMC2_CMD,
GPIO42_MMC2_CLK,
/* MMC3 */
GPIO165_MMC3_DAT7,
GPIO162_MMC3_DAT6,
GPIO166_MMC3_DAT5,
GPIO163_MMC3_DAT4,
GPIO167_MMC3_DAT3,
GPIO164_MMC3_DAT2,
GPIO168_MMC3_DAT1,
GPIO111_MMC3_DAT0,
GPIO112_MMC3_CMD,
GPIO151_MMC3_CLK,
};
static struct pxa_gpio_platform_data mmp2_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static struct regulator_consumer_supply max8649_supply[] = {
REGULATOR_SUPPLY("vcc_core", NULL),
};
static struct regulator_init_data max8649_init_data = {
.constraints = {
.name = "vcc_core range",
.min_uV = 1150000,
.max_uV = 1280000,
.always_on = 1,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = 1,
.consumer_supplies = &max8649_supply[0],
};
static struct max8649_platform_data jasper_max8649_info = {
.mode = 2, /* VID1 = 1, VID0 = 0 */
.extclk = 0,
.ramp_timing = MAX8649_RAMP_32MV,
.regulator = &max8649_init_data,
};
static struct max8925_backlight_pdata jasper_backlight_data = {
.dual_string = 0,
};
static struct max8925_power_pdata jasper_power_data = {
.batt_detect = 0, /* can't detect battery by ID pin */
.topoff_threshold = MAX8925_TOPOFF_THR_10PER,
.fast_charge = MAX8925_FCHG_1000MA,
};
static struct max8925_platform_data jasper_max8925_info = {
.backlight = &jasper_backlight_data,
.power = &jasper_power_data,
.irq_base = MMP_NR_IRQS,
};
static struct i2c_board_info jasper_twsi1_info[] = {
[0] = {
.type = "max8649",
.addr = 0x60,
.platform_data = &jasper_max8649_info,
},
[1] = {
.type = "max8925",
.addr = 0x3c,
.irq = IRQ_MMP2_PMIC,
.platform_data = &jasper_max8925_info,
},
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
.clk_delay_cycles = 0x1f,
};
static void __init jasper_init(void)
{
mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
/* on-chip devices */
mmp2_add_uart(1);
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&mmp2_device_gpio);
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
regulator_has_full_constraints();
}
MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
.map_io = mmp_map_io,
.nr_irqs = JASPER_NR_IRQS,
.init_irq = mmp2_init_irq,
.init_time = mmp2_timer_init,
.init_machine = jasper_init,
.restart = mmp_restart,
MACHINE_END

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arch/arm/mach-mmp/mfp-mmp2.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MACH_MFP_MMP2_H
#define __ASM_MACH_MFP_MMP2_H
#include "mfp.h"
#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
#define MFP_DRIVE_SLOW (0x2 << 13)
#define MFP_DRIVE_MEDIUM (0x4 << 13)
#define MFP_DRIVE_FAST (0x6 << 13)
/* GPIO */
#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG(GPIO102, AF1)
#define GPIO103_GPIO MFP_CFG(GPIO103, AF1)
#define GPIO104_GPIO MFP_CFG(GPIO104, AF1)
#define GPIO105_GPIO MFP_CFG(GPIO105, AF1)
#define GPIO106_GPIO MFP_CFG(GPIO106, AF1)
#define GPIO107_GPIO MFP_CFG(GPIO107, AF1)
#define GPIO108_GPIO MFP_CFG(GPIO108, AF1)
#define GPIO109_GPIO MFP_CFG(GPIO109, AF1)
#define GPIO110_GPIO MFP_CFG(GPIO110, AF1)
#define GPIO111_GPIO MFP_CFG(GPIO111, AF1)
#define GPIO112_GPIO MFP_CFG(GPIO112, AF1)
#define GPIO113_GPIO MFP_CFG(GPIO113, AF1)
#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
#define GPIO128_GPIO MFP_CFG(GPIO128, AF0)
#define GPIO129_GPIO MFP_CFG(GPIO129, AF0)
#define GPIO130_GPIO MFP_CFG(GPIO130, AF0)
#define GPIO131_GPIO MFP_CFG(GPIO131, AF0)
#define GPIO132_GPIO MFP_CFG(GPIO132, AF0)
#define GPIO133_GPIO MFP_CFG(GPIO133, AF0)
#define GPIO134_GPIO MFP_CFG(GPIO134, AF0)
#define GPIO135_GPIO MFP_CFG(GPIO135, AF0)
#define GPIO136_GPIO MFP_CFG(GPIO136, AF0)
#define GPIO137_GPIO MFP_CFG(GPIO137, AF0)
#define GPIO138_GPIO MFP_CFG(GPIO138, AF0)
#define GPIO139_GPIO MFP_CFG(GPIO139, AF0)
#define GPIO140_GPIO MFP_CFG(GPIO140, AF0)
#define GPIO141_GPIO MFP_CFG(GPIO141, AF0)
#define GPIO142_GPIO MFP_CFG(GPIO142, AF1)
#define GPIO143_GPIO MFP_CFG(GPIO143, AF1)
#define GPIO144_GPIO MFP_CFG(GPIO144, AF1)
#define GPIO145_GPIO MFP_CFG(GPIO145, AF1)
#define GPIO146_GPIO MFP_CFG(GPIO146, AF1)
#define GPIO147_GPIO MFP_CFG(GPIO147, AF1)
#define GPIO148_GPIO MFP_CFG(GPIO148, AF1)
#define GPIO149_GPIO MFP_CFG(GPIO149, AF1)
#define GPIO150_GPIO MFP_CFG(GPIO150, AF1)
#define GPIO151_GPIO MFP_CFG(GPIO151, AF1)
#define GPIO152_GPIO MFP_CFG(GPIO152, AF1)
#define GPIO153_GPIO MFP_CFG(GPIO153, AF1)
#define GPIO154_GPIO MFP_CFG(GPIO154, AF1)
#define GPIO155_GPIO MFP_CFG(GPIO155, AF1)
#define GPIO156_GPIO MFP_CFG(GPIO156, AF1)
#define GPIO157_GPIO MFP_CFG(GPIO157, AF1)
#define GPIO158_GPIO MFP_CFG(GPIO158, AF1)
#define GPIO159_GPIO MFP_CFG(GPIO159, AF1)
#define GPIO160_GPIO MFP_CFG(GPIO160, AF1)
#define GPIO161_GPIO MFP_CFG(GPIO161, AF1)
#define GPIO162_GPIO MFP_CFG(GPIO162, AF1)
#define GPIO163_GPIO MFP_CFG(GPIO163, AF1)
#define GPIO164_GPIO MFP_CFG(GPIO164, AF1)
#define GPIO165_GPIO MFP_CFG(GPIO165, AF1)
#define GPIO166_GPIO MFP_CFG(GPIO166, AF1)
#define GPIO167_GPIO MFP_CFG(GPIO167, AF1)
#define GPIO168_GPIO MFP_CFG(GPIO168, AF1)
/* DFI */
#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)
#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0)
#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0)
#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0)
#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0)
#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0)
#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0)
#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0)
#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0)
#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0)
#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0)
#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0)
#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0)
#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0)
#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0)
#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0)
#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0)
#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0)
#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0)
#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0)
#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0)
#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0)
#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0)
#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0)
/* Static Memory Controller */
#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0)
#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0)
#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0)
#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0)
#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0)
#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0)
#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0)
/* Ethernet */
#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2)
/* UART1 */
#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1)
#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1)
#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1)
#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1)
#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1)
#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1)
/* UART2 */
#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1)
#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1)
#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1)
#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1)
/* UART3 */
#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1)
#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1)
#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1)
#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1)
/* MMC1 */
#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST)
#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST)
#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST)
#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST)
#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST)
#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST)
#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST)
#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST)
#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST)
#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST)
#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST)
#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST)
/*MMC2*/
#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST)
#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST)
#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST)
#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST)
#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST)
#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST)
/*MMC3*/
#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST)
#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST)
#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST)
#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST)
#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST)
#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST)
#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST)
#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST)
#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST)
#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST)
/* LCD */
#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST)
#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST)
#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST)
#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST)
#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST)
#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST)
#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST)
#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST)
#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST)
#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST)
#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST)
#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST)
#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST)
#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST)
#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST)
#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST)
#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST)
#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST)
#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST)
#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST)
#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST)
#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST)
#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST)
#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST)
#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST)
#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST)
#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST)
#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST)
#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST)
#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST)
#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST)
#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST)
#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST)
#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST)
/*LCD TV path*/
#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST)
#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST)
#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST)
#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST)
#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST)
#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST)
#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST)
#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST)
#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST)
#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST)
#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST)
#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST)
/* I2C */
#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW)
#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW)
#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW)
#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW)
#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW)
#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW)
#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW)
#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW)
#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW)
#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW)
/* SSPA1 */
#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1)
#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1)
#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1)
#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1)
#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1)
#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1)
/* SSPA2 */
#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1)
#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1)
#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1)
#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1)
/* Keypad */
#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1)
#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1)
#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1)
#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1)
/* CAMERA */
#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST)
#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST)
#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST)
#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST)
#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST)
#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST)
#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST)
#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST)
#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST)
#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST)
#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST)
#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST)
/* PMIC */
#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0)
#endif /* __ASM_MACH_MFP_MMP2_H */

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arch/arm/mach-mmp/mfp-pxa168.h
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@ -1,355 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MACH_MFP_PXA168_H
#define __ASM_MACH_MFP_PXA168_H
#include "mfp.h"
#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
#define MFP_DRIVE_SLOW (0x1 << 13)
#define MFP_DRIVE_MEDIUM (0x2 << 13)
#define MFP_DRIVE_FAST (0x3 << 13)
#undef MFP_CFG
#undef MFP_CFG_DRV
#define MFP_CFG(pin, af) \
(MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM)
#define MFP_CFG_DRV(pin, af, drv) \
(MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv)
/* GPIO */
#define GPIO0_GPIO MFP_CFG(GPIO0, AF5)
#define GPIO1_GPIO MFP_CFG(GPIO1, AF5)
#define GPIO2_GPIO MFP_CFG(GPIO2, AF5)
#define GPIO3_GPIO MFP_CFG(GPIO3, AF5)
#define GPIO4_GPIO MFP_CFG(GPIO4, AF5)
#define GPIO5_GPIO MFP_CFG(GPIO5, AF5)
#define GPIO6_GPIO MFP_CFG(GPIO6, AF5)
#define GPIO7_GPIO MFP_CFG(GPIO7, AF5)
#define GPIO8_GPIO MFP_CFG(GPIO8, AF5)
#define GPIO9_GPIO MFP_CFG(GPIO9, AF5)
#define GPIO10_GPIO MFP_CFG(GPIO10, AF5)
#define GPIO11_GPIO MFP_CFG(GPIO11, AF5)
#define GPIO12_GPIO MFP_CFG(GPIO12, AF5)
#define GPIO13_GPIO MFP_CFG(GPIO13, AF5)
#define GPIO14_GPIO MFP_CFG(GPIO14, AF5)
#define GPIO15_GPIO MFP_CFG(GPIO15, AF5)
#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG(GPIO17, AF5)
#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG(GPIO19, AF5)
#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG(GPIO21, AF5)
#define GPIO22_GPIO MFP_CFG(GPIO22, AF5)
#define GPIO23_GPIO MFP_CFG(GPIO23, AF5)
#define GPIO24_GPIO MFP_CFG(GPIO24, AF5)
#define GPIO25_GPIO MFP_CFG(GPIO25, AF5)
#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG(GPIO27, AF5)
#define GPIO28_GPIO MFP_CFG(GPIO28, AF5)
#define GPIO29_GPIO MFP_CFG(GPIO29, AF5)
#define GPIO30_GPIO MFP_CFG(GPIO30, AF5)
#define GPIO31_GPIO MFP_CFG(GPIO31, AF5)
#define GPIO32_GPIO MFP_CFG(GPIO32, AF5)
#define GPIO33_GPIO MFP_CFG(GPIO33, AF5)
#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
/* DFI */
#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0)
#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0)
#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0)
#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0)
#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0)
#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0)
#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0)
#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0)
#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0)
#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0)
#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0)
#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0)
#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0)
#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0)
#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0)
#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0)
#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0)
#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0)
#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0)
#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0)
/* NAND */
#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1)
#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0)
#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0)
#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0)
#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0)
#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1)
#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1)
/* Static Memory Controller */
#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3)
#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2)
#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2)
#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3)
#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0)
#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2)
#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0)
#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0)
#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0)
#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0)
#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0)
#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2)
#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2)
#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2)
/* Compact Flash */
#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3)
#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3)
#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3)
#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3)
#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3)
#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3)
#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3)
#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3)
#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3)
#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3)
/* UART */
#define GPIO8_UART3_TXD MFP_CFG(GPIO8, AF2)
#define GPIO9_UART3_RXD MFP_CFG(GPIO9, AF2)
#define GPIO1O_UART3_CTS MFP_CFG(GPIO10, AF2)
#define GPIO11_UART3_RTS MFP_CFG(GPIO11, AF2)
#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2)
#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2)
#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST)
#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST)
#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST)
#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST)
#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1)
#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2)
#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1)
#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2)
#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1)
#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2)
#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1)
#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2)
/* MMC1 */
#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1)
#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1)
#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1)
#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1)
#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1)
#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1)
#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1)
#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1)
#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1)
#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1)
#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1)
#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1)
/* MMC2 */
#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
/* MMC4 */
#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
/* LCD */
#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1)
#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1)
#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1)
#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1)
#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1)
#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1)
#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1)
#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1)
#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1)
#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1)
#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1)
#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1)
#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1)
#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1)
#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1)
#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1)
#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1)
#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1)
#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1)
#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1)
#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1)
#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1)
#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1)
#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1)
#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1)
#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1)
#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1)
#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1)
#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1)
#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1)
/* I2C */
#define GPIO105_CI2C_SDA MFP_CFG(GPIO105, AF1)
#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1)
/* I2S */
#define GPIO113_I2S_MCLK MFP_CFG(GPIO113, AF6)
#define GPIO114_I2S_FRM MFP_CFG(GPIO114, AF1)
#define GPIO115_I2S_BCLK MFP_CFG(GPIO115, AF1)
#define GPIO116_I2S_RXD MFP_CFG(GPIO116, AF2)
#define GPIO116_I2S_TXD MFP_CFG(GPIO116, AF1)
#define GPIO117_I2S_TXD MFP_CFG(GPIO117, AF2)
/* PWM */
#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1)
#define GPIO97_PWM2_OUT MFP_CFG(GPIO97, AF1)
#define GPIO98_PWM1_OUT MFP_CFG(GPIO98, AF1)
#define GPIO104_PWM4_OUT MFP_CFG(GPIO104, AF1)
#define GPIO106_PWM2_OUT MFP_CFG(GPIO106, AF2)
#define GPIO74_PWM4_OUT MFP_CFG(GPIO74, AF2)
#define GPIO75_PWM3_OUT MFP_CFG(GPIO75, AF2)
#define GPIO76_PWM2_OUT MFP_CFG(GPIO76, AF2)
#define GPIO77_PWM1_OUT MFP_CFG(GPIO77, AF2)
#define GPIO82_PWM4_OUT MFP_CFG(GPIO82, AF2)
#define GPIO83_PWM3_OUT MFP_CFG(GPIO83, AF2)
#define GPIO84_PWM2_OUT MFP_CFG(GPIO84, AF2)
#define GPIO85_PWM1_OUT MFP_CFG(GPIO85, AF2)
#define GPIO84_PWM1_OUT MFP_CFG(GPIO84, AF4)
#define GPIO122_PWM3_OUT MFP_CFG(GPIO122, AF3)
#define GPIO123_PWM1_OUT MFP_CFG(GPIO123, AF1)
#define GPIO124_PWM2_OUT MFP_CFG(GPIO124, AF1)
#define GPIO125_PWM3_OUT MFP_CFG(GPIO125, AF1)
#define GPIO126_PWM4_OUT MFP_CFG(GPIO126, AF1)
#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2)
#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3)
/* Keypad */
#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7)
#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7)
#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7)
#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
/* Fast Ethernet */
#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5)
#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5)
#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5)
#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5)
#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5)
#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5)
#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5)
#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5)
#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5)
#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5)
#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5)
#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5)
#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5)
#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5)
#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
/* SSP2 */
#define GPIO107_SSP2_RXD MFP_CFG(GPIO107, AF4)
#define GPIO108_SSP2_TXD MFP_CFG(GPIO108, AF4)
#define GPIO111_SSP2_CLK MFP_CFG(GPIO111, AF4)
#define GPIO112_SSP2_FRM MFP_CFG(GPIO112, AF4)
#endif /* __ASM_MACH_MFP_PXA168_H */

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arch/arm/mach-mmp/mfp-pxa910.h
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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __ASM_MACH_MFP_PXA910_H
#define __ASM_MACH_MFP_PXA910_H
#include "mfp.h"
#define MFP_DRIVE_VERY_SLOW (0x0 << 13)
#define MFP_DRIVE_SLOW (0x2 << 13)
#define MFP_DRIVE_MEDIUM (0x4 << 13)
#define MFP_DRIVE_FAST (0x6 << 13)
/* UART2 */
#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6)
#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6)
/* UART3 */
#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4)
#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4)
/*IRDA*/
#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0)
/* SMC */
#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0)
#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0)
#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0)
#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1)
#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1)
/* I2C */
#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2)
#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2)
/* SSP1 (I2S) */
#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM)
#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM)
#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM)
#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM)
#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM)
#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM)
#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM)
/* DFI */
#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0)
#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0)
#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0)
#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0)
#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0)
#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0)
#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0)
#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0)
#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0)
#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0)
#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0)
#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0)
#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0)
#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0)
#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0)
#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0)
#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0)
#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1)
#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0)
#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1)
#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1)
#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0)
/*keypad*/
#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1)
#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1)
#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1)
#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1)
#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1)
#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1)
#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1)
#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1)
#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1)
#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1)
#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1)
#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1)
#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1)
#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1)
#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1)
#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1)
#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1)
#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1)
#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1)
#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1)
/* LCD */
#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1)
#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1)
#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1)
#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1)
#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1)
#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1)
#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1)
#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1)
#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1)
#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1)
#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1)
#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1)
#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1)
#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1)
#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1)
#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1)
#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1)
#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1)
#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1)
#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1)
#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1)
#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1)
#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1)
#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1)
#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1)
#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1)
#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1)
#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1)
#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3)
#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3)
#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3)
#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3)
#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0)
/*smart panel*/
#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0)
#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0)
#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0)
/*1wire*/
#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3)
/*CCIC*/
#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM)
#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM)
#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM)
#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM)
#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM)
#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM)
#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM)
#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM)
#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM)
#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM)
#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM)
#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM)
/* MMC1 */
#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM)
#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM)
#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM)
#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM)
#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM)
#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM)
#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM)
#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM)
#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM)
#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM)
#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM)
#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM)
/* PWM */
#define GPIO27_PWM3_AF2 MFP_CFG(GPIO27, AF2)
#define GPIO51_PWM2_OUT MFP_CFG(GPIO51, AF2)
#define GPIO117_PWM1_OUT MFP_CFG(GPIO117, AF2)
#define GPIO118_PWM2_OUT MFP_CFG(GPIO118, AF2)
#define GPIO119_PWM3_OUT MFP_CFG(GPIO119, AF2)
#define GPIO120_PWM4_OUT MFP_CFG(GPIO120, AF2)
#endif /* __ASM_MACH MFP_PXA910_H */

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arch/arm/mach-mmp/teton_bga.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/teton_bga.c
*
* Support for the Marvell PXA168 Teton BGA Development Platform.
*
* Author: Mark F. Brown <mark.brown314@gmail.com>
*
* This code is based on aspenite.c
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/input.h>
#include <linux/platform_data/keypad-pxa27x.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include "addr-map.h"
#include "mfp-pxa168.h"
#include "pxa168.h"
#include "teton_bga.h"
#include "irqs.h"
#include "common.h"
static unsigned long teton_bga_pin_config[] __initdata = {
/* UART1 */
GPIO107_UART1_TXD,
GPIO108_UART1_RXD,
/* Keypad */
GPIO109_KP_MKIN1,
GPIO110_KP_MKIN0,
GPIO111_KP_MKOUT7,
GPIO112_KP_MKOUT6,
/* I2C Bus */
GPIO105_CI2C_SDA,
GPIO106_CI2C_SCL,
/* RTC */
GPIO78_GPIO,
};
static struct pxa_gpio_platform_data pxa168_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static unsigned int teton_bga_matrix_key_map[] = {
KEY(0, 6, KEY_ESC),
KEY(0, 7, KEY_ENTER),
KEY(1, 6, KEY_LEFT),
KEY(1, 7, KEY_RIGHT),
};
static struct matrix_keymap_data teton_bga_matrix_keymap_data = {
.keymap = teton_bga_matrix_key_map,
.keymap_size = ARRAY_SIZE(teton_bga_matrix_key_map),
};
static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
.matrix_key_rows = 2,
.matrix_key_cols = 8,
.matrix_keymap_data = &teton_bga_matrix_keymap_data,
.debounce_interval = 30,
};
static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("ds1337", 0x68),
.irq = MMP_GPIO_TO_IRQ(RTC_INT_GPIO)
},
};
static void __init teton_bga_init(void)
{
mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
/* on-chip devices */
pxa168_add_uart(1);
pxa168_add_keypad(&teton_bga_keypad_info);
pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_device_register(&pxa168_device_gpio);
}
MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
.map_io = mmp_map_io,
.nr_irqs = MMP_NR_IRQS,
.init_irq = pxa168_init_irq,
.init_time = pxa168_timer_init,
.init_machine = teton_bga_init,
.restart = pxa168_restart,
MACHINE_END

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arch/arm/mach-mmp/teton_bga.h
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@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Support for the Marvell PXA168 Teton BGA Development Platform.
*/
#ifndef __ASM_MACH_TETON_BGA_H
#define __ASM_MACH_TETON_BGA_H
/* GPIOs */
#define MMC_PWENA_GPIO 27
#define USBHPENB_GPIO 55
#define RTC_INT_GPIO 78
#define LCD_VBLK_EN_GPIO 79
#define LCD_DVDD_EN_GPIO 80
#define RST_WIFI_GPIO 81
#define CF_PWEN_GPIO 82
#define USB_OC_GPIO 83
#define PWM_GPIO 84
#define USBHPENA_GPIO 85
#define TS_INT_GPIO 86
#define CIR_GPIO 108
#endif /* __ASM_MACH_TETON_BGA_H */

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arch/arm/mach-mmp/ttc_dkb.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/arch/arm/mach-mmp/ttc_dkb.c
*
* Support for the Marvell PXA910-based TTC_DKB Development Platform.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>
#include <linux/interrupt.h>
#include <linux/platform_data/pca953x.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/mfd/88pm860x.h>
#include <linux/platform_data/mv_usb.h>
#include <linux/spi/spi.h>
#include <linux/delay.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include "addr-map.h"
#include "mfp-pxa910.h"
#include "pxa910.h"
#include "irqs.h"
#include "regs-usb.h"
#include "common.h"
#define TTCDKB_GPIO_EXT0(x) (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 : \
((x < 16) ? x : 15)))
#define TTCDKB_GPIO_EXT1(x) (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
((x < 16) ? x : 15)))
/*
* 16 board interrupts -- MAX7312 GPIO expander
* 16 board interrupts -- PCA9575 GPIO expander
* 24 board interrupts -- 88PM860x PMIC
*/
#define TTCDKB_NR_IRQS (MMP_NR_IRQS + 16 + 16 + 24)
static unsigned long ttc_dkb_pin_config[] __initdata = {
/* UART2 */
GPIO47_UART2_RXD,
GPIO48_UART2_TXD,
/* DFI */
DF_IO0_ND_IO0,
DF_IO1_ND_IO1,
DF_IO2_ND_IO2,
DF_IO3_ND_IO3,
DF_IO4_ND_IO4,
DF_IO5_ND_IO5,
DF_IO6_ND_IO6,
DF_IO7_ND_IO7,
DF_IO8_ND_IO8,
DF_IO9_ND_IO9,
DF_IO10_ND_IO10,
DF_IO11_ND_IO11,
DF_IO12_ND_IO12,
DF_IO13_ND_IO13,
DF_IO14_ND_IO14,
DF_IO15_ND_IO15,
DF_nCS0_SM_nCS2_nCS0,
DF_ALE_SM_WEn_ND_ALE,
DF_CLE_SM_OEn_ND_CLE,
DF_WEn_DF_WEn,
DF_REn_DF_REn,
DF_RDY0_DF_RDY0,
};
static struct pxa_gpio_platform_data pxa910_gpio_pdata = {
.irq_base = MMP_GPIO_TO_IRQ(0),
};
static struct mtd_partition ttc_dkb_onenand_partitions[] = {
{
.name = "bootloader",
.offset = 0,
.size = SZ_1M,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "reserved",
.offset = MTDPART_OFS_APPEND,
.size = SZ_8M,
.mask_flags = MTD_WRITEABLE,
}, {
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = (SZ_2M + SZ_1M),
.mask_flags = 0,
}, {
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = SZ_32M + SZ_16M,
.mask_flags = 0,
}
};
static struct onenand_platform_data ttc_dkb_onenand_info = {
.parts = ttc_dkb_onenand_partitions,
.nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions),
};
static struct resource ttc_dkb_resource_onenand[] = {
[0] = {
.start = SMC_CS0_PHYS_BASE,
.end = SMC_CS0_PHYS_BASE + SZ_1M,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device ttc_dkb_device_onenand = {
.name = "onenand-flash",
.id = -1,
.resource = ttc_dkb_resource_onenand,
.num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand),
.dev = {
.platform_data = &ttc_dkb_onenand_info,
},
};
static struct platform_device *ttc_dkb_devices[] = {
&pxa910_device_gpio,
&pxa910_device_rtc,
&ttc_dkb_device_onenand,
};
static struct pca953x_platform_data max7312_data[] = {
{
.gpio_base = TTCDKB_GPIO_EXT0(0),
.irq_base = MMP_NR_IRQS,
},
};
static struct pm860x_platform_data ttc_dkb_pm8607_info = {
.irq_base = IRQ_BOARD_START,
};
static struct i2c_board_info ttc_dkb_i2c_info[] = {
{
.type = "88PM860x",
.addr = 0x34,
.platform_data = &ttc_dkb_pm8607_info,
.irq = IRQ_PXA910_PMIC_INT,
},
{
.type = "max7312",
.addr = 0x23,
.irq = MMP_GPIO_TO_IRQ(80),
.platform_data = &max7312_data,
},
};
#if IS_ENABLED(CONFIG_USB_SUPPORT)
#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
static struct mv_usb_platform_data ttc_usb_pdata = {
.vbus = NULL,
.mode = MV_USB_MODE_OTG,
.otg_force_a_bus_req = 1,
.phy_init = pxa_usb_phy_init,
.phy_deinit = pxa_usb_phy_deinit,
.set_vbus = NULL,
};
#endif
#endif
#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
static struct pxa3xx_nand_platform_data dkb_nand_info = {};
#endif
#if IS_ENABLED(CONFIG_MMP_DISP)
/* path config */
#define CFG_IOPADMODE(iopad) (iopad) /* 0x0 ~ 0xd */
#define SCLK_SOURCE_SELECT(x) (x << 30) /* 0x0 ~ 0x3 */
/* link config */
#define CFG_DUMBMODE(mode) (mode << 28) /* 0x0 ~ 0x6*/
static struct mmp_mach_path_config dkb_disp_config[] = {
[0] = {
.name = "mmp-parallel",
.overlay_num = 2,
.output_type = PATH_OUT_PARALLEL,
.path_config = CFG_IOPADMODE(0x1)
| SCLK_SOURCE_SELECT(0x1),
.link_config = CFG_DUMBMODE(0x2),
},
};
static struct mmp_mach_plat_info dkb_disp_info = {
.name = "mmp-disp",
.clk_name = "disp0",
.path_num = 1,
.paths = dkb_disp_config,
};
static struct mmp_buffer_driver_mach_info dkb_fb_info = {
.name = "mmp-fb",
.path_name = "mmp-parallel",
.overlay_id = 0,
.dmafetch_id = 1,
.default_pixfmt = PIXFMT_RGB565,
};
static void dkb_tpo_panel_power(int on)
{
int err;
u32 spi_reset = mfp_to_gpio(MFP_PIN_GPIO106);
if (on) {
err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET");
if (err) {
pr_err("failed to request GPIO for TPO LCD RESET\n");
return;
}
gpio_direction_output(spi_reset, 0);
udelay(100);
gpio_set_value(spi_reset, 1);
gpio_free(spi_reset);
} else {
err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET");
if (err) {
pr_err("failed to request LCD RESET gpio\n");
return;
}
gpio_set_value(spi_reset, 0);
gpio_free(spi_reset);
}
}
static struct mmp_mach_panel_info dkb_tpo_panel_info = {
.name = "tpo-hvga",
.plat_path_name = "mmp-parallel",
.plat_set_onoff = dkb_tpo_panel_power,
};
static struct spi_board_info spi_board_info[] __initdata = {
{
.modalias = "tpo-hvga",
.platform_data = &dkb_tpo_panel_info,
.bus_num = 5,
}
};
static void __init add_disp(void)
{
mmp_register_device(&pxa910_device_disp,
&dkb_disp_info, sizeof(dkb_disp_info));
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
mmp_register_device(&pxa910_device_fb,
&dkb_fb_info, sizeof(dkb_fb_info));
mmp_register_device(&pxa910_device_panel,
&dkb_tpo_panel_info, sizeof(dkb_tpo_panel_info));
}
#endif
static void __init ttc_dkb_init(void)
{
mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
/* on-chip devices */
pxa910_add_uart(1);
#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL)
pxa910_add_nand(&dkb_nand_info);
#endif
/* off-chip devices */
pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata,
sizeof(struct pxa_gpio_platform_data));
platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
#if IS_ENABLED(CONFIG_USB_SUPPORT)
#if IS_ENABLED(CONFIG_PHY_PXA_USB)
platform_device_register(&pxa168_device_usb_phy);
#endif
#if IS_ENABLED(CONFIG_USB_MV_UDC)
pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2o);
#endif
#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O)
pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2oehci);
#endif
#if IS_ENABLED(CONFIG_USB_MV_OTG)
pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata;
platform_device_register(&pxa168_device_u2ootg);
#endif
#endif
#if IS_ENABLED(CONFIG_MMP_DISP)
add_disp();
#endif
}
MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
.map_io = mmp_map_io,
.nr_irqs = TTCDKB_NR_IRQS,
.init_irq = pxa910_init_irq,
.init_time = pxa910_timer_init,
.init_machine = ttc_dkb_init,
.restart = mmp_restart,
MACHINE_END