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Mediatek DRM Next for Linux 5.10
1. Move Mediatek HDMI PHY driver from DRM folder to PHY folder 2. Convert mtk-dpi to drm_bridge API 3. Disable tmds on mt2701 -----BEGIN PGP SIGNATURE----- iQJMBAABCgA2FiEEACwLKSDmq+9RDv5P4cpzo8lZTiQFAl9f6twYHGNodW5rdWFu Zy5odUBrZXJuZWwub3JnAAoJEOHKc6PJWU4k+FwQAItKwQieI/hfjE6+8AI4atW+ e7HV3BQ2MkctIqeis/RZv1ubOtVFbpy7U0ndOU2ejFTLs92qBDgf5x91ywFZBK9P 4n5BnU7uMmkhSSUJFfGAutADCONq2AsCCp7SNwqhCk865cYowbc0RBbE/6FyXPHB XbmGKKyU61F0X/MdIXPIC37zUNIr0aynMHqo2dirhpQd3wKDxUcWaRzC3VC7tmA+ OgR0KQJondBtNeW0lHXv/beAyLbqQgMwlNbGNG0omWjnsO92BvmFyK1W1WYUMCRx UMzbjzFV8SHn2ewVbGaNj8hgfnp3qA1CZ7qNcTZdYt3cEvj8xB8iGP4kRdzcCKh7 iqHqMQNrC+vWPtL6uNl/9MkO6mXpXL0bQj2tPkMf2tR33VbMS+L700QRgoC6PPrE JTGb0/UEPrdL/wghJHOOJ+oYo/gaHjPgWZZ/FmPdS3VNZ9DqG1xGmzRdNpixCFKV RK185UKiGgoUfv14kGWRu9YXS0I+nGl4tzj3xXCM0uxXEL0z7rxWhMEEkWzQfHqf 87hsbt8WD0/TAdEhUYdqfClKbxzlTMAiIbH9rTJii/wAXtP2mSx8fjoM3K4mr5k4 wx6RFPVpJkD7/CPNsJHuhicwn3AiBOlnEO9tfYqhqSOez1nFF9HaLur4XLpq4W0c KqALebgZ9zM9UnJGlhIY =NyM2 -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-next-5.10' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 5.10 1. Move Mediatek HDMI PHY driver from DRM folder to PHY folder 2. Convert mtk-dpi to drm_bridge API 3. Disable tmds on mt2701 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20200914231227.30500-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie
commit
06c14f5c2d
@ -43,7 +43,7 @@ Required properties (all function blocks):
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"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
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"mediatek,<chip>-disp-mutex" - display mutex
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"mediatek,<chip>-disp-od" - overdrive
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the supported chips are mt2701, mt2712 and mt8173.
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the supported chips are mt2701, mt7623, mt2712 and mt8173.
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- reg: Physical base address and length of the function block register space
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- interrupts: The interrupt signal from the function block (required, except for
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merge and split function blocks).
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@ -7,7 +7,7 @@ output bus.
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Required properties:
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- compatible: "mediatek,<chip>-dpi"
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the supported chips are mt2701 , mt8173 and mt8183.
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the supported chips are mt2701, mt7623, mt8173 and mt8183.
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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@ -7,7 +7,7 @@ channel output.
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Required properties:
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- compatible: "mediatek,<chip>-dsi"
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the supported chips are mt2701, mt8173 and mt8183.
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- the supported chips are mt2701, mt7623, mt8173 and mt8183.
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
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Required properties:
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- compatible: "mediatek,<chip>-mipi-tx"
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the supported chips are mt2701, mt8173 and mt8183.
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- the supported chips are mt2701, 7623, mt8173 and mt8183.
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- reg: Physical base address and length of the controller's registers
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- clocks: PLL reference clock
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- clock-output-names: name of the output clock line to the DSI encoder
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@ -6,6 +6,7 @@ its parallel input.
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Required properties:
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- compatible: Should be "mediatek,<chip>-hdmi".
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- the supported chips are mt2701, mt7623 and mt8173
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clocks
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@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.
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Required properties:
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- compatible: Should be "mediatek,<chip>-cec"
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- the supported chips are mt7623 and mt8173
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- reg: Physical base address and length of the controller's registers
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- interrupts: The interrupt signal from the function block.
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- clocks: device clock
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@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.
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Required properties:
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- compatible: Should be "mediatek,<chip>-hdmi-ddc"
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- the supported chips are mt7623 and mt8173
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- reg: Physical base address and length of the controller's registers
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- clocks: device clock
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- clock-names: Should be "ddc-i2c".
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@ -56,6 +59,7 @@ output and drives the HDMI pads.
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Required properties:
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- compatible: "mediatek,<chip>-hdmi-phy"
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- the supported chips are mt2701, mt7623 and mt8173
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- reg: Physical base address and length of the module's registers
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- clocks: PLL reference clock
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- clock-names: must contain "pll_ref"
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@ -5827,6 +5827,7 @@ L: dri-devel@lists.freedesktop.org
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S: Supported
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F: Documentation/devicetree/bindings/display/mediatek/
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F: drivers/gpu/drm/mediatek/
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F: drivers/phy/mediatek/phy-mtk-hdmi*
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DRM DRIVERS FOR NVIDIA TEGRA
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M: Thierry Reding <thierry.reding@gmail.com>
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@ -24,6 +24,6 @@ config DRM_MEDIATEK_HDMI
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tristate "DRM HDMI Support for Mediatek SoCs"
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depends on DRM_MEDIATEK
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select SND_SOC_HDMI_CODEC if SND_SOC
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select GENERIC_PHY
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select PHY_MTK_HDMI
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help
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DRM/KMS HDMI driver for Mediatek SoCs
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@ -19,9 +19,6 @@ obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o
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mediatek-drm-hdmi-objs := mtk_cec.o \
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mtk_hdmi.o \
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mtk_hdmi_ddc.o \
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mtk_mt2701_hdmi_phy.o \
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mtk_mt8173_hdmi_phy.o \
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mtk_hdmi_phy.o
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mtk_hdmi_ddc.o
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obj-$(CONFIG_DRM_MEDIATEK_HDMI) += mediatek-drm-hdmi.o
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@ -64,7 +64,8 @@ enum mtk_dpi_out_color_format {
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struct mtk_dpi {
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struct mtk_ddp_comp ddp_comp;
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struct drm_encoder encoder;
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struct drm_bridge *bridge;
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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void __iomem *regs;
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struct device *dev;
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struct clk *engine_clk;
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@ -83,9 +84,9 @@ struct mtk_dpi {
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int refcount;
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};
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static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
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static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
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{
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return container_of(e, struct mtk_dpi, encoder);
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return container_of(b, struct mtk_dpi, bridge);
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}
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enum mtk_dpi_polarity {
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@ -521,50 +522,53 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
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return 0;
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}
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static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static void mtk_dpi_encoder_destroy(struct drm_encoder *encoder)
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{
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return true;
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drm_encoder_cleanup(encoder);
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}
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static void mtk_dpi_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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static const struct drm_encoder_funcs mtk_dpi_encoder_funcs = {
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.destroy = mtk_dpi_encoder_destroy,
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};
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static int mtk_dpi_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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return drm_bridge_attach(bridge->encoder, dpi->next_bridge,
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&dpi->bridge, flags);
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}
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static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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drm_mode_copy(&dpi->mode, adjusted_mode);
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}
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static void mtk_dpi_encoder_disable(struct drm_encoder *encoder)
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static void mtk_dpi_bridge_disable(struct drm_bridge *bridge)
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{
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struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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mtk_dpi_power_off(dpi);
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}
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static void mtk_dpi_encoder_enable(struct drm_encoder *encoder)
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static void mtk_dpi_bridge_enable(struct drm_bridge *bridge)
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{
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struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
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struct mtk_dpi *dpi = bridge_to_dpi(bridge);
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mtk_dpi_power_on(dpi);
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mtk_dpi_set_display_mode(dpi, &dpi->mode);
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}
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static int mtk_dpi_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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return 0;
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}
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static const struct drm_encoder_helper_funcs mtk_dpi_encoder_helper_funcs = {
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.mode_fixup = mtk_dpi_encoder_mode_fixup,
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.mode_set = mtk_dpi_encoder_mode_set,
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.disable = mtk_dpi_encoder_disable,
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.enable = mtk_dpi_encoder_enable,
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.atomic_check = mtk_dpi_atomic_check,
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static const struct drm_bridge_funcs mtk_dpi_bridge_funcs = {
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.attach = mtk_dpi_bridge_attach,
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.mode_set = mtk_dpi_bridge_mode_set,
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.disable = mtk_dpi_bridge_disable,
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.enable = mtk_dpi_bridge_enable,
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};
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static void mtk_dpi_start(struct mtk_ddp_comp *comp)
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@ -605,12 +609,10 @@ static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
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dev_err(dev, "Failed to initialize decoder: %d\n", ret);
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goto err_unregister;
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}
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drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
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/* Currently DPI0 is fixed to be driven by OVL1 */
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dpi->encoder.possible_crtcs = BIT(1);
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dpi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm_dev, dpi->ddp_comp);
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ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0);
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ret = drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, 0);
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if (ret) {
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dev_err(dev, "Failed to attach bridge: %d\n", ret);
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goto err_cleanup;
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@ -770,11 +772,11 @@ static int mtk_dpi_probe(struct platform_device *pdev)
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}
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ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
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NULL, &dpi->bridge);
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NULL, &dpi->next_bridge);
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if (ret)
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return ret;
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dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge->of_node);
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dev_info(dev, "Found bridge node: %pOF\n", dpi->next_bridge->of_node);
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comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
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if (comp_id < 0) {
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@ -791,8 +793,15 @@ static int mtk_dpi_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, dpi);
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dpi->bridge.funcs = &mtk_dpi_bridge_funcs;
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dpi->bridge.of_node = dev->of_node;
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dpi->bridge.type = DRM_MODE_CONNECTOR_DPI;
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drm_bridge_add(&dpi->bridge);
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ret = component_add(dev, &mtk_dpi_component_ops);
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if (ret) {
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drm_bridge_remove(&dpi->bridge);
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dev_err(dev, "Failed to add component: %d\n", ret);
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return ret;
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}
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@ -802,7 +811,10 @@ static int mtk_dpi_probe(struct platform_device *pdev)
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static int mtk_dpi_remove(struct platform_device *pdev)
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{
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struct mtk_dpi *dpi = platform_get_drvdata(pdev);
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component_del(&pdev->dev, &mtk_dpi_component_ops);
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drm_bridge_remove(&dpi->bridge);
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return 0;
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}
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@ -13,6 +13,8 @@
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include <drm/drm_print.h>
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#include "mtk_drm_drv.h"
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#include "mtk_drm_plane.h"
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#include "mtk_drm_ddp_comp.h"
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@ -412,6 +414,22 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
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[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
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};
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static bool mtk_drm_find_comp_in_ddp(struct mtk_ddp_comp ddp_comp,
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const enum mtk_ddp_comp_id *path,
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unsigned int path_len)
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{
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unsigned int i;
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if (path == NULL)
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return false;
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for (i = 0U; i < path_len; i++)
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if (ddp_comp.id == path[i])
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return true;
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return false;
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}
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int mtk_ddp_comp_get_id(struct device_node *node,
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enum mtk_ddp_comp_type comp_type)
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{
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@ -427,6 +445,26 @@ int mtk_ddp_comp_get_id(struct device_node *node,
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return -EINVAL;
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}
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unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
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struct mtk_ddp_comp ddp_comp)
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{
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struct mtk_drm_private *private = drm->dev_private;
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unsigned int ret = 0;
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if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->main_path, private->data->main_len))
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ret = BIT(0);
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else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->ext_path,
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private->data->ext_len))
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ret = BIT(1);
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else if (mtk_drm_find_comp_in_ddp(ddp_comp, private->data->third_path,
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private->data->third_len))
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ret = BIT(2);
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else
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DRM_INFO("Failed to find comp in ddp table\n");
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return ret;
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}
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int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
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struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
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const struct mtk_ddp_comp_funcs *funcs)
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@ -202,6 +202,8 @@ static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
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|
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int mtk_ddp_comp_get_id(struct device_node *node,
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enum mtk_ddp_comp_type comp_type);
|
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unsigned int mtk_drm_find_possible_crtc_by_comp(struct drm_device *drm,
|
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struct mtk_ddp_comp ddp_comp);
|
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int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
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struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
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const struct mtk_ddp_comp_funcs *funcs);
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|
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@ -74,6 +74,19 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
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DDP_COMPONENT_DPI0,
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};
|
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|
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static const enum mtk_ddp_comp_id mt7623_mtk_ddp_main[] = {
|
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DDP_COMPONENT_OVL0,
|
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DDP_COMPONENT_RDMA0,
|
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DDP_COMPONENT_COLOR0,
|
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DDP_COMPONENT_BLS,
|
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DDP_COMPONENT_DPI0,
|
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};
|
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|
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static const enum mtk_ddp_comp_id mt7623_mtk_ddp_ext[] = {
|
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DDP_COMPONENT_RDMA1,
|
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DDP_COMPONENT_DSI0,
|
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};
|
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|
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static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
|
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DDP_COMPONENT_OVL0,
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DDP_COMPONENT_COLOR0,
|
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@ -127,6 +140,14 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
|
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.shadow_register = true,
|
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};
|
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|
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static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
|
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.main_path = mt7623_mtk_ddp_main,
|
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.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
|
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.ext_path = mt7623_mtk_ddp_ext,
|
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.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
|
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.shadow_register = true,
|
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};
|
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|
||||
static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
|
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.main_path = mt2712_mtk_ddp_main,
|
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.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
|
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@ -422,6 +443,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
|
||||
static const struct of_device_id mtk_drm_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt2701-mmsys",
|
||||
.data = &mt2701_mmsys_driver_data},
|
||||
{ .compatible = "mediatek,mt7623-mmsys",
|
||||
.data = &mt7623_mmsys_driver_data},
|
||||
{ .compatible = "mediatek,mt2712-mmsys",
|
||||
.data = &mt2712_mmsys_driver_data},
|
||||
{ .compatible = "mediatek,mt8173-mmsys",
|
||||
|
||||
@ -970,11 +970,7 @@ static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Currently display data paths are statically assigned to a crtc each.
|
||||
* crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
|
||||
*/
|
||||
dsi->encoder.possible_crtcs = 1;
|
||||
dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
|
||||
|
||||
ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
|
||||
DRM_BRIDGE_ATTACH_NO_CONNECTOR);
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of.h>
|
||||
@ -145,11 +146,16 @@ struct hdmi_audio_param {
|
||||
struct hdmi_codec_params codec_params;
|
||||
};
|
||||
|
||||
struct mtk_hdmi_conf {
|
||||
bool tz_disabled;
|
||||
};
|
||||
|
||||
struct mtk_hdmi {
|
||||
struct drm_bridge bridge;
|
||||
struct drm_bridge *next_bridge;
|
||||
struct drm_connector conn;
|
||||
struct device *dev;
|
||||
const struct mtk_hdmi_conf *conf;
|
||||
struct phy *phy;
|
||||
struct device *cec_dev;
|
||||
struct i2c_adapter *ddc_adpt;
|
||||
@ -234,7 +240,6 @@ static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
|
||||
static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
struct mtk_hdmi_phy *hdmi_phy = phy_get_drvdata(hdmi->phy);
|
||||
|
||||
/*
|
||||
* MT8173 HDMI hardware has an output control bit to enable/disable HDMI
|
||||
@ -242,7 +247,7 @@ static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
|
||||
* The ARM trusted firmware provides an API for the HDMI driver to set
|
||||
* this control bit to enable HDMI output in supervisor mode.
|
||||
*/
|
||||
if (hdmi_phy->conf && hdmi_phy->conf->tz_disabled)
|
||||
if (hdmi->conf && hdmi->conf->tz_disabled)
|
||||
regmap_update_bits(hdmi->sys_regmap,
|
||||
hdmi->sys_offset + HDMI_SYS_CFG20,
|
||||
0x80008005, enable ? 0x80000005 : 0x8000);
|
||||
@ -1723,6 +1728,7 @@ static int mtk_drm_hdmi_probe(struct platform_device *pdev)
|
||||
return -ENOMEM;
|
||||
|
||||
hdmi->dev = dev;
|
||||
hdmi->conf = of_device_get_match_data(dev);
|
||||
|
||||
ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
|
||||
if (ret)
|
||||
@ -1803,8 +1809,16 @@ static int mtk_hdmi_resume(struct device *dev)
|
||||
static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
|
||||
mtk_hdmi_suspend, mtk_hdmi_resume);
|
||||
|
||||
static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
|
||||
.tz_disabled = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt8173-hdmi", },
|
||||
{ .compatible = "mediatek,mt2701-hdmi",
|
||||
.data = &mtk_hdmi_conf_mt2701,
|
||||
},
|
||||
{ .compatible = "mediatek,mt8173-hdmi",
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
@ -1819,7 +1833,6 @@ static struct platform_driver mtk_hdmi_driver = {
|
||||
};
|
||||
|
||||
static struct platform_driver * const mtk_hdmi_drivers[] = {
|
||||
&mtk_hdmi_phy_driver,
|
||||
&mtk_hdmi_ddc_driver,
|
||||
&mtk_cec_driver,
|
||||
&mtk_hdmi_driver,
|
||||
|
||||
@ -5,7 +5,6 @@
|
||||
*/
|
||||
#ifndef _MTK_HDMI_CTRL_H
|
||||
#define _MTK_HDMI_CTRL_H
|
||||
#include "mtk_hdmi_phy.h"
|
||||
|
||||
struct platform_driver;
|
||||
|
||||
|
||||
@ -35,3 +35,10 @@ config PHY_MTK_XSPHY
|
||||
Enable this to support the SuperSpeedPlus XS-PHY transceiver for
|
||||
USB3.1 GEN2 controllers on MediaTek chips. The driver supports
|
||||
multiple USB2.0, USB3.1 GEN2 ports.
|
||||
|
||||
config PHY_MTK_HDMI
|
||||
tristate "MediaTek HDMI-PHY Driver"
|
||||
depends on ARCH_MEDIATEK && OF
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Support HDMI PHY for Mediatek SoCs.
|
||||
|
||||
@ -6,3 +6,8 @@
|
||||
obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
|
||||
obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
|
||||
obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
|
||||
|
||||
phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
|
||||
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
|
||||
phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt8173.o
|
||||
obj-$(CONFIG_PHY_MTK_HDMI) += phy-mtk-hdmi-drv.o
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
* Author: Chunhui Dai <chunhui.dai@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mtk_hdmi_phy.h"
|
||||
#include "phy-mtk-hdmi.h"
|
||||
|
||||
#define HDMI_CON0 0x00
|
||||
#define RG_HDMITX_DRV_IBIAS 0
|
||||
@ -237,8 +237,8 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
|
||||
}
|
||||
|
||||
struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = {
|
||||
.tz_disabled = true,
|
||||
.flags = CLK_SET_RATE_GATE,
|
||||
.pll_default_off = true,
|
||||
.hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops,
|
||||
.hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds,
|
||||
.hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
|
||||
@ -4,7 +4,7 @@
|
||||
* Author: Jie Qiu <jie.qiu@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mtk_hdmi_phy.h"
|
||||
#include "phy-mtk-hdmi.h"
|
||||
|
||||
#define HDMI_CON0 0x00
|
||||
#define RG_HDMITX_PLL_EN BIT(31)
|
||||
@ -4,7 +4,7 @@
|
||||
* Author: Jie Qiu <jie.qiu@mediatek.com>
|
||||
*/
|
||||
|
||||
#include "mtk_hdmi_phy.h"
|
||||
#include "phy-mtk-hdmi.h"
|
||||
|
||||
static int mtk_hdmi_phy_power_on(struct phy *phy);
|
||||
static int mtk_hdmi_phy_power_off(struct phy *phy);
|
||||
@ -184,6 +184,9 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(phy_provider);
|
||||
}
|
||||
|
||||
if (hdmi_phy->conf->pll_default_off)
|
||||
hdmi_phy->conf->hdmi_phy_disable_tmds(hdmi_phy);
|
||||
|
||||
return of_clk_add_provider(dev->of_node, of_clk_src_simple_get,
|
||||
hdmi_phy->pll);
|
||||
}
|
||||
@ -205,6 +208,7 @@ struct platform_driver mtk_hdmi_phy_driver = {
|
||||
.of_match_table = mtk_hdmi_phy_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(mtk_hdmi_phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek HDMI PHY Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -20,8 +20,8 @@
|
||||
struct mtk_hdmi_phy;
|
||||
|
||||
struct mtk_hdmi_phy_conf {
|
||||
bool tz_disabled;
|
||||
unsigned long flags;
|
||||
bool pll_default_off;
|
||||
const struct clk_ops *hdmi_phy_clk_ops;
|
||||
void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
|
||||
void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
|
||||
@ -50,7 +50,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
||||
u32 val, u32 mask);
|
||||
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
|
||||
|
||||
extern struct platform_driver mtk_hdmi_phy_driver;
|
||||
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
|
||||
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user