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octeontx2-pf: Attach NIX and NPA block LFs
For a PF to function as a NIC, NPA (for Rx buffers, Tx descriptors etc) and NIX (for rcv, send and completion queues) are the minimum resources needed. So request admin function (AF) to attach one each of NIX and NPA block LFs (local functions). Only AF can configure a LF's contexts, so request AF to allocate memory for NPA aura/pool and NIX RQ/SQ/CQ HW contexts. Upon receiving response, save some of the HW constants like number of pointers per stack page, size of send queue buffer (SQBs, where SQEs are queued by HW) e.t.c which are later used to initialize queues. A HW context here is like a state machine maintained for a descriptor queue. eg size, head/tail pointers, irq etc etc. HW maintains this in memory. Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sunil Goutham
David S. Miller
parent
5a6d7c9dae
commit
05fcc9e089
@ -13,6 +13,173 @@
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#include "otx2_reg.h"
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#include "otx2_common.h"
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#include "otx2_struct.h"
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int otx2_config_nix(struct otx2_nic *pfvf)
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{
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struct nix_lf_alloc_req *nixlf;
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struct nix_lf_alloc_rsp *rsp;
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int err;
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pfvf->qset.xqe_size = NIX_XQESZ_W16 ? 128 : 512;
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/* Get memory to put this msg */
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nixlf = otx2_mbox_alloc_msg_nix_lf_alloc(&pfvf->mbox);
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if (!nixlf)
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return -ENOMEM;
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/* Set RQ/SQ/CQ counts */
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nixlf->rq_cnt = pfvf->hw.rx_queues;
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nixlf->sq_cnt = pfvf->hw.tx_queues;
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nixlf->cq_cnt = pfvf->qset.cq_cnt;
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nixlf->xqe_sz = NIX_XQESZ_W16;
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/* We don't know absolute NPA LF idx attached.
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* AF will replace 'RVU_DEFAULT_PF_FUNC' with
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* NPA LF attached to this RVU PF/VF.
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*/
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nixlf->npa_func = RVU_DEFAULT_PF_FUNC;
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/* Disable alignment pad, enable L2 length check,
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* enable L4 TCP/UDP checksum verification.
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*/
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nixlf->rx_cfg = BIT_ULL(33) | BIT_ULL(35) | BIT_ULL(37);
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err = otx2_sync_mbox_msg(&pfvf->mbox);
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if (err)
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return err;
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rsp = (struct nix_lf_alloc_rsp *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0,
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&nixlf->hdr);
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if (IS_ERR(rsp))
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return PTR_ERR(rsp);
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if (rsp->qints < 1)
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return -ENXIO;
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return rsp->hdr.rc;
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}
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int otx2_config_npa(struct otx2_nic *pfvf)
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{
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struct otx2_qset *qset = &pfvf->qset;
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struct npa_lf_alloc_req *npalf;
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struct otx2_hw *hw = &pfvf->hw;
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int aura_cnt;
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/* Pool - Stack of free buffer pointers
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* Aura - Alloc/frees pointers from/to pool for NIX DMA.
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*/
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if (!hw->pool_cnt)
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return -EINVAL;
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qset->pool = devm_kzalloc(pfvf->dev, sizeof(struct otx2_pool) *
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hw->pool_cnt, GFP_KERNEL);
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if (!qset->pool)
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return -ENOMEM;
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/* Get memory to put this msg */
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npalf = otx2_mbox_alloc_msg_npa_lf_alloc(&pfvf->mbox);
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if (!npalf)
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return -ENOMEM;
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/* Set aura and pool counts */
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npalf->nr_pools = hw->pool_cnt;
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aura_cnt = ilog2(roundup_pow_of_two(hw->pool_cnt));
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npalf->aura_sz = (aura_cnt >= ilog2(128)) ? (aura_cnt - 6) : 1;
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return otx2_sync_mbox_msg(&pfvf->mbox);
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}
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int otx2_detach_resources(struct mbox *mbox)
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{
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struct rsrc_detach *detach;
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otx2_mbox_lock(mbox);
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detach = otx2_mbox_alloc_msg_detach_resources(mbox);
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if (!detach) {
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otx2_mbox_unlock(mbox);
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return -ENOMEM;
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}
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/* detach all */
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detach->partial = false;
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/* Send detach request to AF */
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otx2_mbox_msg_send(&mbox->mbox, 0);
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otx2_mbox_unlock(mbox);
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return 0;
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}
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int otx2_attach_npa_nix(struct otx2_nic *pfvf)
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{
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struct rsrc_attach *attach;
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struct msg_req *msix;
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int err;
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otx2_mbox_lock(&pfvf->mbox);
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/* Get memory to put this msg */
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attach = otx2_mbox_alloc_msg_attach_resources(&pfvf->mbox);
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if (!attach) {
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otx2_mbox_unlock(&pfvf->mbox);
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return -ENOMEM;
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}
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attach->npalf = true;
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attach->nixlf = true;
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/* Send attach request to AF */
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err = otx2_sync_mbox_msg(&pfvf->mbox);
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if (err) {
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otx2_mbox_unlock(&pfvf->mbox);
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return err;
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}
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/* Get NPA and NIX MSIX vector offsets */
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msix = otx2_mbox_alloc_msg_msix_offset(&pfvf->mbox);
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if (!msix) {
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otx2_mbox_unlock(&pfvf->mbox);
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return -ENOMEM;
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}
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err = otx2_sync_mbox_msg(&pfvf->mbox);
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if (err) {
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otx2_mbox_unlock(&pfvf->mbox);
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return err;
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}
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otx2_mbox_unlock(&pfvf->mbox);
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if (pfvf->hw.npa_msixoff == MSIX_VECTOR_INVALID ||
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pfvf->hw.nix_msixoff == MSIX_VECTOR_INVALID) {
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dev_err(pfvf->dev,
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"RVUPF: Invalid MSIX vector offset for NPA/NIX\n");
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return -EINVAL;
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}
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return 0;
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}
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/* Mbox message handlers */
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void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
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struct npa_lf_alloc_rsp *rsp)
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{
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pfvf->hw.stack_pg_ptrs = rsp->stack_pg_ptrs;
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pfvf->hw.stack_pg_bytes = rsp->stack_pg_bytes;
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}
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void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
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struct nix_lf_alloc_rsp *rsp)
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{
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pfvf->hw.sqb_size = rsp->sqb_size;
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pfvf->hw.rx_chan_base = rsp->rx_chan_base;
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pfvf->hw.tx_chan_base = rsp->tx_chan_base;
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}
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void mbox_handler_msix_offset(struct otx2_nic *pfvf,
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struct msix_offset_rsp *rsp)
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{
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pfvf->hw.npa_msixoff = rsp->npa_msixoff;
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pfvf->hw.nix_msixoff = rsp->nix_msixoff;
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}
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#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
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int __weak \
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@ -25,6 +25,17 @@
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#define NAME_SIZE 32
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struct otx2_pool {
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struct qmem *stack;
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};
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struct otx2_qset {
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#define OTX2_MAX_CQ_CNT 64
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u16 cq_cnt;
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u16 xqe_size; /* Size of CQE i.e 128 or 512 bytes */
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struct otx2_pool *pool;
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};
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struct mbox {
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struct otx2_mbox mbox;
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struct work_struct mbox_wrk;
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@ -42,8 +53,19 @@ struct otx2_hw {
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u16 rx_queues;
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u16 tx_queues;
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u16 max_queues;
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u16 pool_cnt;
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/* NPA */
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u32 stack_pg_ptrs; /* No of ptrs per stack page */
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u32 stack_pg_bytes; /* Size of stack page */
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u16 sqb_size;
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u16 rx_chan_base;
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u16 tx_chan_base;
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/* MSI-X */
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u16 npa_msixoff; /* Offset of NPA vectors */
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u16 nix_msixoff; /* Offset of NIX vectors */
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char *irq_name;
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cpumask_var_t *affinity_mask;
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};
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@ -52,6 +74,7 @@ struct otx2_nic {
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void __iomem *reg_base;
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struct net_device *netdev;
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struct otx2_qset qset;
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struct otx2_hw hw;
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struct pci_dev *pdev;
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struct device *dev;
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@ -240,4 +263,17 @@ MBOX_UP_CGX_MESSAGES
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#define RVU_PFVF_FUNC_SHIFT 0
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#define RVU_PFVF_FUNC_MASK 0x3FF
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/* RVU block related APIs */
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int otx2_attach_npa_nix(struct otx2_nic *pfvf);
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int otx2_detach_resources(struct mbox *mbox);
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int otx2_config_npa(struct otx2_nic *pfvf);
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int otx2_config_nix(struct otx2_nic *pfvf);
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/* Mbox handlers */
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void mbox_handler_msix_offset(struct otx2_nic *pfvf,
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struct msix_offset_rsp *rsp);
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void mbox_handler_npa_lf_alloc(struct otx2_nic *pfvf,
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struct npa_lf_alloc_rsp *rsp);
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void mbox_handler_nix_lf_alloc(struct otx2_nic *pfvf,
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struct nix_lf_alloc_rsp *rsp);
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#endif /* OTX2_COMMON_H */
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@ -114,6 +114,15 @@ static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf,
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case MBOX_MSG_READY:
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pf->pcifunc = msg->pcifunc;
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break;
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case MBOX_MSG_MSIX_OFFSET:
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mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg);
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break;
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case MBOX_MSG_NPA_LF_ALLOC:
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mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg);
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break;
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case MBOX_MSG_NIX_LF_ALLOC:
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mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg);
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break;
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default:
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if (msg->rc)
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dev_err(pf->dev,
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@ -372,9 +381,20 @@ static int otx2_set_real_num_queues(struct net_device *netdev,
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static int otx2_open(struct net_device *netdev)
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{
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struct otx2_nic *pf = netdev_priv(netdev);
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int err = 0;
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netif_carrier_off(netdev);
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return 0;
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pf->qset.cq_cnt = pf->hw.rx_queues + pf->hw.tx_queues;
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/* NPA init */
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err = otx2_config_npa(pf);
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if (err)
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return err;
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/* NIX init */
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return otx2_config_nix(pf);
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}
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static int otx2_stop(struct net_device *netdev)
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@ -405,6 +425,31 @@ static int otx2_check_pf_usable(struct otx2_nic *nic)
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return 0;
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}
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static int otx2_realloc_msix_vectors(struct otx2_nic *pf)
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{
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struct otx2_hw *hw = &pf->hw;
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int num_vec, err;
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/* NPA interrupts are inot registered, so alloc only
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* upto NIX vector offset.
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*/
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num_vec = hw->nix_msixoff;
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#define NIX_LF_CINT_VEC_START 0x40
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num_vec += NIX_LF_CINT_VEC_START + hw->max_queues;
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otx2_disable_mbox_intr(pf);
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pci_free_irq_vectors(hw->pdev);
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pci_free_irq_vectors(hw->pdev);
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err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX);
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if (err < 0) {
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dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n",
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__func__, num_vec);
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return err;
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}
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return otx2_register_mbox_intr(pf, false);
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}
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static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct device *dev = &pdev->dev;
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@ -435,7 +480,7 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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pci_set_master(pdev);
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/* Set number of queues */
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qcount = min_t(int, num_online_cpus(), num_online_cpus());
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qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT);
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netdev = alloc_etherdev_mqs(sizeof(*pf), qcount, qcount);
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if (!netdev) {
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@ -497,20 +542,33 @@ static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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if (err)
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goto err_mbox_destroy;
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err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
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/* Request AF to attach NPA and NIX LFs to this PF.
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* NIX and NPA LFs are needed for this PF to function as a NIC.
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*/
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err = otx2_attach_npa_nix(pf);
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if (err)
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goto err_disable_mbox_intr;
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err = otx2_realloc_msix_vectors(pf);
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if (err)
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goto err_detach_rsrc;
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err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues);
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if (err)
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goto err_detach_rsrc;
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netdev->netdev_ops = &otx2_netdev_ops;
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err = register_netdev(netdev);
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if (err) {
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dev_err(dev, "Failed to register netdevice\n");
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goto err_disable_mbox_intr;
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goto err_detach_rsrc;
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}
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return 0;
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err_detach_rsrc:
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otx2_detach_resources(&pf->mbox);
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err_disable_mbox_intr:
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otx2_disable_mbox_intr(pf);
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err_mbox_destroy:
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@ -536,6 +594,7 @@ static void otx2_remove(struct pci_dev *pdev)
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pf = netdev_priv(netdev);
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unregister_netdev(netdev);
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otx2_detach_resources(&pf->mbox);
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otx2_disable_mbox_intr(pf);
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otx2_pfaf_mbox_destroy(pf);
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pci_free_irq_vectors(pf->pdev);
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20
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
Normal file
20
drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h
Normal file
@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell OcteonTx2 RVU Ethernet driver
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*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OTX2_STRUCT_H
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#define OTX2_STRUCT_H
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/* NIX WQE/CQE size 128 byte or 512 byte */
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enum nix_cqesz_e {
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NIX_XQESZ_W64 = 0x0,
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NIX_XQESZ_W16 = 0x1,
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};
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#endif /* OTX2_STRUCT_H */
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