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qed: utilize FW 8.10.10.0
This new firmware for the qed* adpaters fixes several issues: - Better blocking of malicious VFs. - After FLR, Tx-switching [internal routing] of packets might be incorrect. - Deletion of unicast MAC filters would sometime have side-effect of corrupting the MAC filters configred for a device. It also contains fixes for future qed* drivers that *hopefully* would be sent for review in the near future. In addition, it would allow driver some new functionality, including: - Allowing PF/VF driver compaitibility with old drivers [running pre-8.10.5.0 firmware]. - Better debug facilities. This would also bump the qed* driver versions to 8.10.9.20. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
parent
75d67207bf
commit
05fafbfb3d
@ -26,7 +26,7 @@
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#include "qed_hsi.h"
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extern const struct qed_common_ops qed_common_ops_pass;
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#define DRV_MODULE_VERSION "8.7.1.20"
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#define DRV_MODULE_VERSION "8.10.9.20"
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#define MAX_HWFNS_PER_DEVICE (4)
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#define NAME_SIZE 16
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@ -772,6 +772,9 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
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concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);
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qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);
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qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);
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qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0);
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qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1);
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qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0);
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}
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/* pretend to original PF */
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qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
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@ -782,34 +785,8 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
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static int qed_hw_init_port(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, int hw_mode)
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{
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int rc = 0;
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rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode);
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if (rc)
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return rc;
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if (hw_mode & (1 << MODE_MF_SI)) {
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u8 pf_id = 0;
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if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
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DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
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"PF[%08x] is first eth on engine\n", pf_id);
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/* We should have configured BIT for ppfid, i.e., the
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* relative function number in the port. But there's a
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* bug in LLH in BB where the ppfid is actually engine
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* based, so we need to take this into account.
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*/
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qed_wr(p_hwfn, p_ptt,
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NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id);
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}
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/* Take the protocol-based hit vector if there is a hit,
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* otherwise take the other vector.
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*/
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2);
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}
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return rc;
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return qed_init_run(p_hwfn, p_ptt, PHASE_PORT,
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p_hwfn->port_id, hw_mode);
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}
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static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
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@ -878,21 +855,6 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
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/* Pure runtime initializations - directly to the HW */
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qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
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if (hw_mode & (1 << MODE_MF_SI)) {
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u8 pf_id = 0;
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u32 val = 0;
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if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) {
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if (p_hwfn->rel_pf_id == pf_id) {
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DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
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"PF[%d] is first ETH on engine\n",
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pf_id);
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val = 1;
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}
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qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val);
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}
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}
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if (b_hw_start) {
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/* enable interrupts */
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qed_int_igu_enable(p_hwfn, p_ptt, int_mode);
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File diff suppressed because it is too large
Load Diff
@ -534,7 +534,7 @@ int qed_init_fw_data(struct qed_dev *cdev, const u8 *data)
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/* First Dword contains metadata and should be skipped */
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buf_hdr = (struct bin_buffer_hdr *)(data + sizeof(u32));
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offset = buf_hdr[BIN_BUF_FW_VER_INFO].offset;
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offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
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fw->fw_ver_info = (struct fw_ver_info *)(data + offset);
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offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
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@ -802,34 +802,6 @@ static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
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return size;
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}
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int qed_hw_init_first_eth(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 *p_pf)
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{
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struct public_func shmem_info;
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int i;
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/* Find first Ethernet interface in port */
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for (i = 0; i < NUM_OF_ENG_PFS(p_hwfn->cdev);
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i += p_hwfn->cdev->num_ports_in_engines) {
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qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
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MCP_PF_ID_BY_REL(p_hwfn, i));
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if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
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continue;
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if ((shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK) ==
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FUNC_MF_CFG_PROTOCOL_ETHERNET) {
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*p_pf = (u8)i;
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return 0;
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}
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}
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DP_NOTICE(p_hwfn,
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"Failed to find on port an ethernet interface in MF_SI mode\n");
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return -EINVAL;
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}
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static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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struct qed_mcp_function_info *p_info;
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@ -500,6 +500,4 @@ int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn,
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struct qed_mcp_link_state *p_link,
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u8 min_bw);
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int qed_hw_init_first_eth(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 *p_pf);
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#endif
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@ -116,8 +116,14 @@
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0x1009c4UL
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#define QM_REG_PF_EN \
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0x2f2ea4UL
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#define TCFC_REG_WEAK_ENABLE_VF \
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0x2d0704UL
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#define TCFC_REG_STRONG_ENABLE_PF \
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0x2d0708UL
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#define TCFC_REG_STRONG_ENABLE_VF \
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0x2d070cUL
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#define CCFC_REG_WEAK_ENABLE_VF \
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0x2e0704UL
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#define CCFC_REG_STRONG_ENABLE_PF \
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0x2e0708UL
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#define PGLUE_B_REG_PGL_ADDR_88_F0 \
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@ -1280,6 +1280,13 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
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memset(resp, 0, sizeof(*resp));
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/* Write the PF version so that VF would know which version
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* is supported - might be later overriden. This guarantees that
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* VF could recognize legacy PF based on lack of versions in reply.
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*/
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pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
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pfdev_info->minor_fp_hsi = ETH_HSI_VER_MINOR;
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/* Validate FW compatibility */
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if (req->vfdev_info.eth_fp_hsi_major != ETH_HSI_VER_MAJOR) {
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DP_INFO(p_hwfn,
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@ -1289,12 +1296,6 @@ static void qed_iov_vf_mbx_acquire(struct qed_hwfn *p_hwfn,
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req->vfdev_info.eth_fp_hsi_minor,
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ETH_HSI_VER_MAJOR, ETH_HSI_VER_MINOR);
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/* Write the PF version so that VF would know which version
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* is supported.
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*/
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pfdev_info->major_fp_hsi = ETH_HSI_VER_MAJOR;
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pfdev_info->minor_fp_hsi = ETH_HSI_VER_MINOR;
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goto out;
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}
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@ -25,7 +25,7 @@
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#define QEDE_MAJOR_VERSION 8
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#define QEDE_MINOR_VERSION 10
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#define QEDE_REVISION_VERSION 1
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#define QEDE_REVISION_VERSION 9
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#define QEDE_ENGINEERING_VERSION 20
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#define DRV_MODULE_VERSION __stringify(QEDE_MAJOR_VERSION) "." \
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__stringify(QEDE_MINOR_VERSION) "." \
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@ -5,28 +5,83 @@
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* (GPL) Version 2, available from the file COPYING in the main directory of
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* this source tree.
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*/
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#ifndef _COMMON_HSI_H
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#define _COMMON_HSI_H
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#include <linux/bitops.h>
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#include <linux/slab.h>
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/* dma_addr_t manip */
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#define DMA_LO(x) ((u32)(((dma_addr_t)(x)) & 0xffffffff))
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#define DMA_HI(x) ((u32)(((dma_addr_t)(x)) >> 32))
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#define DMA_LO_LE(x) cpu_to_le32(DMA_LO(x))
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#define DMA_HI_LE(x) cpu_to_le32(DMA_HI(x))
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/* It's assumed that whoever includes this has previously included an hsi
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* file defining the regpair.
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*/
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#define DMA_REGPAIR_LE(x, val) (x).hi = DMA_HI_LE((val)); \
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(x).lo = DMA_LO_LE((val))
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#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
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#define HILO_DMA(hi, lo) HILO_GEN(hi, lo, dma_addr_t)
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#define HILO_64(hi, lo) HILO_GEN(hi, lo, u64)
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#define HILO_DMA_REGPAIR(regpair) (HILO_DMA(regpair.hi, regpair.lo))
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#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
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#ifndef __COMMON_HSI__
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#define __COMMON_HSI__
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#define CORE_SPQE_PAGE_SIZE_BYTES 4096
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#define X_FINAL_CLEANUP_AGG_INT 1
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#define EVENT_RING_PAGE_SIZE_BYTES 4096
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#define NUM_OF_GLOBAL_QUEUES 128
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#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
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#define ISCSI_CDU_TASK_SEG_TYPE 0
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#define RDMA_CDU_TASK_SEG_TYPE 1
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#define FW_ASSERT_GENERAL_ATTN_IDX 32
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#define MAX_PINNED_CCFC 32
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/* Queue Zone sizes in bytes */
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#define TSTORM_QZONE_SIZE 8
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#define MSTORM_QZONE_SIZE 0
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#define MSTORM_QZONE_SIZE 16
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#define USTORM_QZONE_SIZE 8
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#define XSTORM_QZONE_SIZE 8
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#define YSTORM_QZONE_SIZE 0
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#define PSTORM_QZONE_SIZE 0
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#define ETH_MAX_NUM_RX_QUEUES_PER_VF 16
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#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
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#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
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#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
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#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
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/********************************/
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/* CORE (LIGHT L2) FW CONSTANTS */
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/********************************/
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#define CORE_LL2_MAX_RAMROD_PER_CON 8
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#define CORE_LL2_TX_BD_PAGE_SIZE_BYTES 4096
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#define CORE_LL2_RX_BD_PAGE_SIZE_BYTES 4096
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#define CORE_LL2_RX_CQE_PAGE_SIZE_BYTES 4096
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#define CORE_LL2_RX_NUM_NEXT_PAGE_BDS 1
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#define CORE_LL2_TX_MAX_BDS_PER_PACKET 12
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#define CORE_SPQE_PAGE_SIZE_BYTES 4096
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#define MAX_NUM_LL2_RX_QUEUES 32
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#define MAX_NUM_LL2_TX_STATS_COUNTERS 32
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#define FW_MAJOR_VERSION 8
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#define FW_MINOR_VERSION 10
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#define FW_REVISION_VERSION 5
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#define FW_REVISION_VERSION 10
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#define FW_ENGINEERING_VERSION 0
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/***********************/
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@ -83,6 +138,17 @@
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#define NUM_OF_LCIDS (320)
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#define NUM_OF_LTIDS (320)
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/* Clock values */
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#define MASTER_CLK_FREQ_E4 (375e6)
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#define STORM_CLK_FREQ_E4 (1000e6)
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#define CLK25M_CLK_FREQ_E4 (25e6)
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/* Global PXP windows (GTT) */
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#define NUM_OF_GTT 19
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#define GTT_DWORD_SIZE_BITS 10
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#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
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#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
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/*****************/
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/* CDU CONSTANTS */
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/*****************/
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@ -90,6 +156,8 @@
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#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
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#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
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#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
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#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
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/*****************/
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/* DQ CONSTANTS */
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/*****************/
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@ -115,6 +183,11 @@
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#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
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#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
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#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
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#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
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#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
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#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
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/* UCM agg val selection (HW) */
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#define DQ_UCM_AGG_VAL_SEL_WORD0 0
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@ -159,13 +232,16 @@
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#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
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/* XCM agg counter flag selection */
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#define DQ_XCM_CORE_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_CORE_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_CORE_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_DQ_CF_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_ETH_TERMINATE_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_ETH_SLOW_PATH_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_TPH_EN_CMD (1 << DQ_XCM_AGG_FLG_SHIFT_CF23)
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#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
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#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
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#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
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#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
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#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
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/* UCM agg counter flag selection (HW) */
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#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
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@ -178,9 +254,45 @@
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#define DQ_UCM_AGG_FLG_SHIFT_RULE1EN 7
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/* UCM agg counter flag selection (FW) */
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#define DQ_UCM_ETH_PMD_TX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF4)
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#define DQ_UCM_ETH_PMD_RX_ARM_CMD (1 << DQ_UCM_AGG_FLG_SHIFT_CF5)
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#define DQ_UCM_ETH_PMD_TX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
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#define DQ_UCM_ETH_PMD_RX_ARM_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
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#define DQ_UCM_ROCE_CQ_ARM_SE_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF4)
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#define DQ_UCM_ROCE_CQ_ARM_CF_CMD BIT(DQ_UCM_AGG_FLG_SHIFT_CF5)
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/* TCM agg counter flag selection (HW) */
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#define DQ_TCM_AGG_FLG_SHIFT_CF0 0
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#define DQ_TCM_AGG_FLG_SHIFT_CF1 1
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#define DQ_TCM_AGG_FLG_SHIFT_CF2 2
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#define DQ_TCM_AGG_FLG_SHIFT_CF3 3
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#define DQ_TCM_AGG_FLG_SHIFT_CF4 4
|
||||
#define DQ_TCM_AGG_FLG_SHIFT_CF5 5
|
||||
#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
|
||||
#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
|
||||
/* TCM agg counter flag selection (FW) */
|
||||
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
|
||||
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
|
||||
|
||||
/* PWM address mapping */
|
||||
#define DQ_PWM_OFFSET_DPM_BASE 0x0
|
||||
#define DQ_PWM_OFFSET_DPM_END 0x27
|
||||
#define DQ_PWM_OFFSET_XCM16_BASE 0x40
|
||||
#define DQ_PWM_OFFSET_XCM32_BASE 0x44
|
||||
#define DQ_PWM_OFFSET_UCM16_BASE 0x48
|
||||
#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
|
||||
#define DQ_PWM_OFFSET_UCM16_4 0x50
|
||||
#define DQ_PWM_OFFSET_TCM16_BASE 0x58
|
||||
#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
|
||||
#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
|
||||
#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
|
||||
#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
|
||||
|
||||
#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
|
||||
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
|
||||
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_16BIT (DQ_PWM_OFFSET_UCM16_4)
|
||||
#define DQ_PWM_OFFSET_UCM_RDMA_INT_TIMEOUT (DQ_PWM_OFFSET_UCM16_BASE + 2)
|
||||
#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
|
||||
#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
|
||||
#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
|
||||
#define DQ_REGION_SHIFT (12)
|
||||
|
||||
/* DPM */
|
||||
@ -214,15 +326,17 @@
|
||||
*/
|
||||
#define CM_TX_PQ_BASE 0x200
|
||||
|
||||
/* number of global Vport/QCN rate limiters */
|
||||
#define MAX_QM_GLOBAL_RLS 256
|
||||
/* QM registers data */
|
||||
#define QM_LINE_CRD_REG_WIDTH 16
|
||||
#define QM_LINE_CRD_REG_SIGN_BIT (1 << (QM_LINE_CRD_REG_WIDTH - 1))
|
||||
#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
|
||||
#define QM_BYTE_CRD_REG_WIDTH 24
|
||||
#define QM_BYTE_CRD_REG_SIGN_BIT (1 << (QM_BYTE_CRD_REG_WIDTH - 1))
|
||||
#define QM_BYTE_CRD_REG_SIGN_BIT BIT((QM_BYTE_CRD_REG_WIDTH - 1))
|
||||
#define QM_WFQ_CRD_REG_WIDTH 32
|
||||
#define QM_WFQ_CRD_REG_SIGN_BIT (1 << (QM_WFQ_CRD_REG_WIDTH - 1))
|
||||
#define QM_WFQ_CRD_REG_SIGN_BIT BIT((QM_WFQ_CRD_REG_WIDTH - 1))
|
||||
#define QM_RL_CRD_REG_WIDTH 32
|
||||
#define QM_RL_CRD_REG_SIGN_BIT (1 << (QM_RL_CRD_REG_WIDTH - 1))
|
||||
#define QM_RL_CRD_REG_SIGN_BIT BIT((QM_RL_CRD_REG_WIDTH - 1))
|
||||
|
||||
/*****************/
|
||||
/* CAU CONSTANTS */
|
||||
@ -287,6 +401,17 @@
|
||||
/* PXP CONSTANTS */
|
||||
/*****************/
|
||||
|
||||
/* Bars for Blocks */
|
||||
#define PXP_BAR_GRC 0
|
||||
#define PXP_BAR_TSDM 0
|
||||
#define PXP_BAR_USDM 0
|
||||
#define PXP_BAR_XSDM 0
|
||||
#define PXP_BAR_MSDM 0
|
||||
#define PXP_BAR_YSDM 0
|
||||
#define PXP_BAR_PSDM 0
|
||||
#define PXP_BAR_IGU 0
|
||||
#define PXP_BAR_DQ 1
|
||||
|
||||
/* PTT and GTT */
|
||||
#define PXP_NUM_PF_WINDOWS 12
|
||||
#define PXP_PER_PF_ENTRY_SIZE 8
|
||||
@ -334,6 +459,52 @@
|
||||
(PXP_EXTERNAL_BAR_GLOBAL_WINDOW_START + \
|
||||
PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
|
||||
|
||||
/* PF BAR */
|
||||
#define PXP_BAR0_START_GRC 0x0000
|
||||
#define PXP_BAR0_GRC_LENGTH 0x1C00000
|
||||
#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
|
||||
PXP_BAR0_GRC_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_IGU 0x1C00000
|
||||
#define PXP_BAR0_IGU_LENGTH 0x10000
|
||||
#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
|
||||
PXP_BAR0_IGU_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_TSDM 0x1C80000
|
||||
#define PXP_BAR0_SDM_LENGTH 0x40000
|
||||
#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
|
||||
#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
|
||||
PXP_BAR0_SDM_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_MSDM 0x1D00000
|
||||
#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
|
||||
PXP_BAR0_SDM_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_USDM 0x1D80000
|
||||
#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
|
||||
PXP_BAR0_SDM_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_XSDM 0x1E00000
|
||||
#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
|
||||
PXP_BAR0_SDM_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_YSDM 0x1E80000
|
||||
#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
|
||||
PXP_BAR0_SDM_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_START_PSDM 0x1F00000
|
||||
#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
|
||||
PXP_BAR0_SDM_LENGTH - 1)
|
||||
|
||||
#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
|
||||
|
||||
/* VF BAR */
|
||||
#define PXP_VF_BAR0 0
|
||||
|
||||
#define PXP_VF_BAR0_START_GRC 0x3E00
|
||||
#define PXP_VF_BAR0_GRC_LENGTH 0x200
|
||||
#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
|
||||
PXP_VF_BAR0_GRC_LENGTH - 1)
|
||||
|
||||
#define PXP_VF_BAR0_START_IGU 0
|
||||
#define PXP_VF_BAR0_IGU_LENGTH 0x3000
|
||||
@ -399,6 +570,20 @@
|
||||
#define PXP_NUM_ILT_RECORDS_BB 7600
|
||||
#define PXP_NUM_ILT_RECORDS_K2 11000
|
||||
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
|
||||
#define PXP_QUEUES_ZONE_MAX_NUM 320
|
||||
/*****************/
|
||||
/* PRM CONSTANTS */
|
||||
/*****************/
|
||||
#define PRM_DMA_PAD_BYTES_NUM 2
|
||||
/******************/
|
||||
/* SDMs CONSTANTS */
|
||||
/******************/
|
||||
#define SDM_OP_GEN_TRIG_NONE 0
|
||||
#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
|
||||
#define SDM_OP_GEN_TRIG_AGG_INT 2
|
||||
#define SDM_OP_GEN_TRIG_LOADER 4
|
||||
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
|
||||
#define SDM_OP_GEN_TRIG_RELEASE_THREAD 7
|
||||
|
||||
#define SDM_COMP_TYPE_NONE 0
|
||||
#define SDM_COMP_TYPE_WAKE_THREAD 1
|
||||
@ -424,6 +609,8 @@
|
||||
/* PRS CONSTANTS */
|
||||
/*****************/
|
||||
|
||||
#define PRS_GFT_CAM_LINES_NO_MATCH 31
|
||||
|
||||
/* Async data KCQ CQE */
|
||||
struct async_data {
|
||||
__le32 cid;
|
||||
@ -440,20 +627,6 @@ struct coalescing_timeset {
|
||||
#define COALESCING_TIMESET_VALID_SHIFT 7
|
||||
};
|
||||
|
||||
struct common_prs_pf_msg_info {
|
||||
__le32 value;
|
||||
#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_MASK 0x1
|
||||
#define COMMON_PRS_PF_MSG_INFO_NPAR_DEFAULT_PF_SHIFT 0
|
||||
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_MASK 0x1
|
||||
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_1_SHIFT 1
|
||||
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_MASK 0x1
|
||||
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_2_SHIFT 2
|
||||
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_MASK 0x1
|
||||
#define COMMON_PRS_PF_MSG_INFO_FW_DEBUG_3_SHIFT 3
|
||||
#define COMMON_PRS_PF_MSG_INFO_RESERVED_MASK 0xFFFFFFF
|
||||
#define COMMON_PRS_PF_MSG_INFO_RESERVED_SHIFT 4
|
||||
};
|
||||
|
||||
struct common_queue_zone {
|
||||
__le16 ring_drv_data_consumer;
|
||||
__le16 reserved;
|
||||
@ -473,6 +646,19 @@ struct vf_pf_channel_eqe_data {
|
||||
struct regpair msg_addr;
|
||||
};
|
||||
|
||||
struct iscsi_eqe_data {
|
||||
__le32 cid;
|
||||
__le16 conn_id;
|
||||
u8 error_code;
|
||||
u8 error_pdu_opcode_reserved;
|
||||
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
|
||||
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
|
||||
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
|
||||
#define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_SHIFT 6
|
||||
#define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
|
||||
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
|
||||
};
|
||||
|
||||
struct malicious_vf_eqe_data {
|
||||
u8 vf_id;
|
||||
u8 err_id;
|
||||
@ -488,6 +674,7 @@ struct initial_cleanup_eqe_data {
|
||||
union event_ring_data {
|
||||
u8 bytes[8];
|
||||
struct vf_pf_channel_eqe_data vf_pf_channel;
|
||||
struct iscsi_eqe_data iscsi_info;
|
||||
struct malicious_vf_eqe_data malicious_vf;
|
||||
struct initial_cleanup_eqe_data vf_init_cleanup;
|
||||
};
|
||||
@ -616,6 +803,52 @@ enum db_dest {
|
||||
MAX_DB_DEST
|
||||
};
|
||||
|
||||
/* Enum of doorbell DPM types */
|
||||
enum db_dpm_type {
|
||||
DPM_LEGACY,
|
||||
DPM_ROCE,
|
||||
DPM_L2_INLINE,
|
||||
DPM_L2_BD,
|
||||
MAX_DB_DPM_TYPE
|
||||
};
|
||||
|
||||
/* Structure for doorbell data, in L2 DPM mode, for 1st db in a DPM burst */
|
||||
struct db_l2_dpm_data {
|
||||
__le16 icid;
|
||||
__le16 bd_prod;
|
||||
__le32 params;
|
||||
#define DB_L2_DPM_DATA_SIZE_MASK 0x3F
|
||||
#define DB_L2_DPM_DATA_SIZE_SHIFT 0
|
||||
#define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
|
||||
#define DB_L2_DPM_DATA_DPM_TYPE_SHIFT 6
|
||||
#define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF
|
||||
#define DB_L2_DPM_DATA_NUM_BDS_SHIFT 8
|
||||
#define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
|
||||
#define DB_L2_DPM_DATA_PKT_SIZE_SHIFT 16
|
||||
#define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
|
||||
#define DB_L2_DPM_DATA_RESERVED0_SHIFT 27
|
||||
#define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
|
||||
#define DB_L2_DPM_DATA_SGE_NUM_SHIFT 28
|
||||
#define DB_L2_DPM_DATA_RESERVED1_MASK 0x1
|
||||
#define DB_L2_DPM_DATA_RESERVED1_SHIFT 31
|
||||
};
|
||||
|
||||
/* Structure for SGE in a DPM doorbell of type DPM_L2_BD */
|
||||
struct db_l2_dpm_sge {
|
||||
struct regpair addr;
|
||||
__le16 nbytes;
|
||||
__le16 bitfields;
|
||||
#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
|
||||
#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
|
||||
#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
|
||||
#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
|
||||
#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
|
||||
#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
|
||||
#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
|
||||
#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
|
||||
__le32 reserved2;
|
||||
};
|
||||
|
||||
/* Structure for doorbell address, in legacy mode */
|
||||
struct db_legacy_addr {
|
||||
__le32 addr;
|
||||
@ -627,6 +860,49 @@ struct db_legacy_addr {
|
||||
#define DB_LEGACY_ADDR_ICID_SHIFT 5
|
||||
};
|
||||
|
||||
/* Structure for doorbell address, in PWM mode */
|
||||
struct db_pwm_addr {
|
||||
__le32 addr;
|
||||
#define DB_PWM_ADDR_RESERVED0_MASK 0x7
|
||||
#define DB_PWM_ADDR_RESERVED0_SHIFT 0
|
||||
#define DB_PWM_ADDR_OFFSET_MASK 0x7F
|
||||
#define DB_PWM_ADDR_OFFSET_SHIFT 3
|
||||
#define DB_PWM_ADDR_WID_MASK 0x3
|
||||
#define DB_PWM_ADDR_WID_SHIFT 10
|
||||
#define DB_PWM_ADDR_DPI_MASK 0xFFFF
|
||||
#define DB_PWM_ADDR_DPI_SHIFT 12
|
||||
#define DB_PWM_ADDR_RESERVED1_MASK 0xF
|
||||
#define DB_PWM_ADDR_RESERVED1_SHIFT 28
|
||||
};
|
||||
|
||||
/* Parameters to RoCE firmware, passed in EDPM doorbell */
|
||||
struct db_roce_dpm_params {
|
||||
__le32 params;
|
||||
#define DB_ROCE_DPM_PARAMS_SIZE_MASK 0x3F
|
||||
#define DB_ROCE_DPM_PARAMS_SIZE_SHIFT 0
|
||||
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_MASK 0x3
|
||||
#define DB_ROCE_DPM_PARAMS_DPM_TYPE_SHIFT 6
|
||||
#define DB_ROCE_DPM_PARAMS_OPCODE_MASK 0xFF
|
||||
#define DB_ROCE_DPM_PARAMS_OPCODE_SHIFT 8
|
||||
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
|
||||
#define DB_ROCE_DPM_PARAMS_WQE_SIZE_SHIFT 16
|
||||
#define DB_ROCE_DPM_PARAMS_RESERVED0_MASK 0x1
|
||||
#define DB_ROCE_DPM_PARAMS_RESERVED0_SHIFT 27
|
||||
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
|
||||
#define DB_ROCE_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
|
||||
#define DB_ROCE_DPM_PARAMS_S_FLG_MASK 0x1
|
||||
#define DB_ROCE_DPM_PARAMS_S_FLG_SHIFT 29
|
||||
#define DB_ROCE_DPM_PARAMS_RESERVED1_MASK 0x3
|
||||
#define DB_ROCE_DPM_PARAMS_RESERVED1_SHIFT 30
|
||||
};
|
||||
|
||||
/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
|
||||
struct db_roce_dpm_data {
|
||||
__le16 icid;
|
||||
__le16 prod_val;
|
||||
struct db_roce_dpm_params params;
|
||||
};
|
||||
|
||||
/* Igu interrupt command */
|
||||
enum igu_int_cmd {
|
||||
IGU_INT_ENABLE = 0,
|
||||
@ -764,6 +1040,19 @@ struct pxp_ptt_entry {
|
||||
struct pxp_pretend_cmd pretend;
|
||||
};
|
||||
|
||||
/* VF Zone A Permission Register. */
|
||||
struct pxp_vf_zone_a_permission {
|
||||
__le32 control;
|
||||
#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
|
||||
#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
|
||||
#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
|
||||
#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
|
||||
#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
|
||||
#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
|
||||
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
|
||||
#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
|
||||
};
|
||||
|
||||
/* RSS hash type */
|
||||
struct rdif_task_context {
|
||||
__le32 initial_ref_tag;
|
||||
@ -831,6 +1120,7 @@ struct rdif_task_context {
|
||||
__le32 reserved2;
|
||||
};
|
||||
|
||||
/* RSS hash type */
|
||||
enum rss_hash_type {
|
||||
RSS_HASH_TYPE_DEFAULT = 0,
|
||||
RSS_HASH_TYPE_IPV4 = 1,
|
||||
@ -942,7 +1232,7 @@ struct tdif_task_context {
|
||||
};
|
||||
|
||||
struct timers_context {
|
||||
__le32 logical_client0;
|
||||
__le32 logical_client_0;
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
|
||||
#define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
|
||||
@ -951,7 +1241,7 @@ struct timers_context {
|
||||
#define TIMERS_CONTEXT_ACTIVELC0_SHIFT 29
|
||||
#define TIMERS_CONTEXT_RESERVED0_MASK 0x3
|
||||
#define TIMERS_CONTEXT_RESERVED0_SHIFT 30
|
||||
__le32 logical_client1;
|
||||
__le32 logical_client_1;
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
|
||||
#define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
|
||||
@ -960,7 +1250,7 @@ struct timers_context {
|
||||
#define TIMERS_CONTEXT_ACTIVELC1_SHIFT 29
|
||||
#define TIMERS_CONTEXT_RESERVED1_MASK 0x3
|
||||
#define TIMERS_CONTEXT_RESERVED1_SHIFT 30
|
||||
__le32 logical_client2;
|
||||
__le32 logical_client_2;
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0xFFFFFFF
|
||||
#define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
|
||||
#define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
|
||||
@ -978,3 +1268,4 @@ struct timers_context {
|
||||
#define TIMERS_CONTEXT_RESERVED3_SHIFT 29
|
||||
};
|
||||
#endif /* __COMMON_HSI__ */
|
||||
#endif
|
||||
|
||||
@ -13,9 +13,12 @@
|
||||
/* ETH FW CONSTANTS */
|
||||
/********************/
|
||||
#define ETH_HSI_VER_MAJOR 3
|
||||
#define ETH_HSI_VER_MINOR 0
|
||||
#define ETH_CACHE_LINE_SIZE 64
|
||||
#define ETH_HSI_VER_MINOR 10
|
||||
|
||||
#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
|
||||
|
||||
#define ETH_CACHE_LINE_SIZE 64
|
||||
#define ETH_RX_CQE_GAP 32
|
||||
#define ETH_MAX_RAMROD_PER_CON 8
|
||||
#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
|
||||
#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
|
||||
@ -24,15 +27,25 @@
|
||||
|
||||
#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
|
||||
#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
|
||||
#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
|
||||
#define ETH_TX_MAX_LSO_HDR_NBD 4
|
||||
#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
|
||||
#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
|
||||
#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
|
||||
#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
|
||||
#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
|
||||
#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
|
||||
#define ETH_TX_MAX_LSO_HDR_BYTES 510
|
||||
#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
|
||||
#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
|
||||
#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
|
||||
#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
|
||||
#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
|
||||
|
||||
#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
|
||||
#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
|
||||
(ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
|
||||
#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
|
||||
(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
|
||||
|
||||
/* Maximum number of buffers, used for RX packet placement */
|
||||
#define ETH_RX_MAX_BUFF_PER_PKT 5
|
||||
@ -59,6 +72,8 @@
|
||||
#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
|
||||
#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
|
||||
|
||||
/* Control frame check constants */
|
||||
#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
|
||||
|
||||
struct eth_tx_1st_bd_flags {
|
||||
u8 bitfields;
|
||||
@ -82,10 +97,10 @@ struct eth_tx_1st_bd_flags {
|
||||
|
||||
/* The parsing information data fo rthe first tx bd of a given packet. */
|
||||
struct eth_tx_data_1st_bd {
|
||||
__le16 vlan;
|
||||
u8 nbds;
|
||||
struct eth_tx_1st_bd_flags bd_flags;
|
||||
__le16 bitfields;
|
||||
__le16 vlan;
|
||||
u8 nbds;
|
||||
struct eth_tx_1st_bd_flags bd_flags;
|
||||
__le16 bitfields;
|
||||
#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
|
||||
#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
|
||||
#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
|
||||
@ -96,7 +111,7 @@ struct eth_tx_data_1st_bd {
|
||||
|
||||
/* The parsing information data for the second tx bd of a given packet. */
|
||||
struct eth_tx_data_2nd_bd {
|
||||
__le16 tunn_ip_size;
|
||||
__le16 tunn_ip_size;
|
||||
__le16 bitfields1;
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
|
||||
#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
|
||||
@ -125,9 +140,14 @@ struct eth_tx_data_2nd_bd {
|
||||
#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
|
||||
};
|
||||
|
||||
/* Firmware data for L2-EDPM packet. */
|
||||
struct eth_edpm_fw_data {
|
||||
struct eth_tx_data_1st_bd data_1st_bd;
|
||||
struct eth_tx_data_2nd_bd data_2nd_bd;
|
||||
__le32 reserved;
|
||||
};
|
||||
|
||||
struct eth_fast_path_cqe_fw_debug {
|
||||
u8 reserved0;
|
||||
u8 reserved1;
|
||||
__le16 reserved2;
|
||||
};
|
||||
|
||||
@ -148,6 +168,17 @@ struct eth_tunnel_parsing_flags {
|
||||
#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
|
||||
};
|
||||
|
||||
/* PMD flow control bits */
|
||||
struct eth_pmd_flow_flags {
|
||||
u8 flags;
|
||||
#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
|
||||
#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
|
||||
#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
|
||||
#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
|
||||
#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
|
||||
#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
|
||||
};
|
||||
|
||||
/* Regular ETH Rx FP CQE. */
|
||||
struct eth_fast_path_rx_reg_cqe {
|
||||
u8 type;
|
||||
@ -166,64 +197,63 @@ struct eth_fast_path_rx_reg_cqe {
|
||||
u8 placement_offset;
|
||||
struct eth_tunnel_parsing_flags tunnel_pars_flags;
|
||||
u8 bd_num;
|
||||
u8 reserved[7];
|
||||
u8 reserved[9];
|
||||
struct eth_fast_path_cqe_fw_debug fw_debug;
|
||||
u8 reserved1[3];
|
||||
u8 flags;
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
|
||||
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
|
||||
struct eth_pmd_flow_flags pmd_flags;
|
||||
};
|
||||
|
||||
/* TPA-continue ETH Rx FP CQE. */
|
||||
struct eth_fast_path_rx_tpa_cont_cqe {
|
||||
u8 type;
|
||||
u8 tpa_agg_index;
|
||||
__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
|
||||
u8 reserved[5];
|
||||
u8 reserved1;
|
||||
__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
|
||||
u8 type;
|
||||
u8 tpa_agg_index;
|
||||
__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
|
||||
u8 reserved;
|
||||
u8 reserved1;
|
||||
__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE];
|
||||
u8 reserved3[3];
|
||||
struct eth_pmd_flow_flags pmd_flags;
|
||||
};
|
||||
|
||||
/* TPA-end ETH Rx FP CQE. */
|
||||
struct eth_fast_path_rx_tpa_end_cqe {
|
||||
u8 type;
|
||||
u8 tpa_agg_index;
|
||||
__le16 total_packet_len;
|
||||
u8 num_of_bds;
|
||||
u8 end_reason;
|
||||
__le16 num_of_coalesced_segs;
|
||||
__le32 ts_delta;
|
||||
__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
|
||||
u8 reserved1[3];
|
||||
u8 reserved2;
|
||||
__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
|
||||
u8 type;
|
||||
u8 tpa_agg_index;
|
||||
__le16 total_packet_len;
|
||||
u8 num_of_bds;
|
||||
u8 end_reason;
|
||||
__le16 num_of_coalesced_segs;
|
||||
__le32 ts_delta;
|
||||
__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE];
|
||||
__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE];
|
||||
__le16 reserved1;
|
||||
u8 reserved2;
|
||||
struct eth_pmd_flow_flags pmd_flags;
|
||||
};
|
||||
|
||||
/* TPA-start ETH Rx FP CQE. */
|
||||
struct eth_fast_path_rx_tpa_start_cqe {
|
||||
u8 type;
|
||||
u8 bitfields;
|
||||
u8 type;
|
||||
u8 bitfields;
|
||||
#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
|
||||
#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
|
||||
#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
|
||||
#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
|
||||
#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
|
||||
#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
|
||||
__le16 seg_len;
|
||||
__le16 seg_len;
|
||||
struct parsing_and_err_flags pars_flags;
|
||||
__le16 vlan_tag;
|
||||
__le32 rss_hash;
|
||||
__le16 len_on_first_bd;
|
||||
u8 placement_offset;
|
||||
__le16 vlan_tag;
|
||||
__le32 rss_hash;
|
||||
__le16 len_on_first_bd;
|
||||
u8 placement_offset;
|
||||
struct eth_tunnel_parsing_flags tunnel_pars_flags;
|
||||
u8 tpa_agg_index;
|
||||
u8 header_len;
|
||||
__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
|
||||
u8 tpa_agg_index;
|
||||
u8 header_len;
|
||||
__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE];
|
||||
struct eth_fast_path_cqe_fw_debug fw_debug;
|
||||
u8 reserved;
|
||||
struct eth_pmd_flow_flags pmd_flags;
|
||||
};
|
||||
|
||||
/* The L4 pseudo checksum mode for Ethernet */
|
||||
@ -245,15 +275,7 @@ struct eth_slow_path_rx_cqe {
|
||||
u8 reserved[25];
|
||||
__le16 echo;
|
||||
u8 reserved1;
|
||||
u8 flags;
|
||||
/* for PMD mode - valid indication */
|
||||
#define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
|
||||
#define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
|
||||
/* for PMD mode - valid toggle indication */
|
||||
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
|
||||
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
|
||||
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
|
||||
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
|
||||
struct eth_pmd_flow_flags pmd_flags;
|
||||
};
|
||||
|
||||
/* union for all ETH Rx CQE types */
|
||||
@ -276,6 +298,11 @@ enum eth_rx_cqe_type {
|
||||
MAX_ETH_RX_CQE_TYPE
|
||||
};
|
||||
|
||||
struct eth_rx_pmd_cqe {
|
||||
union eth_rx_cqe cqe;
|
||||
u8 reserved[ETH_RX_CQE_GAP];
|
||||
};
|
||||
|
||||
enum eth_rx_tunn_type {
|
||||
ETH_RX_NO_TUNN,
|
||||
ETH_RX_TUNN_GENEVE,
|
||||
@ -313,8 +340,8 @@ struct eth_tx_2nd_bd {
|
||||
|
||||
/* The parsing information data for the third tx bd of a given packet. */
|
||||
struct eth_tx_data_3rd_bd {
|
||||
__le16 lso_mss;
|
||||
__le16 bitfields;
|
||||
__le16 lso_mss;
|
||||
__le16 bitfields;
|
||||
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
|
||||
#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
|
||||
#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
|
||||
@ -323,8 +350,8 @@ struct eth_tx_data_3rd_bd {
|
||||
#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
|
||||
#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
|
||||
#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
|
||||
u8 tunn_l4_hdr_start_offset_w;
|
||||
u8 tunn_hdr_size_w;
|
||||
u8 tunn_l4_hdr_start_offset_w;
|
||||
u8 tunn_hdr_size_w;
|
||||
};
|
||||
|
||||
/* The third tx bd of a given packet */
|
||||
@ -355,10 +382,10 @@ struct eth_tx_bd {
|
||||
};
|
||||
|
||||
union eth_tx_bd_types {
|
||||
struct eth_tx_1st_bd first_bd;
|
||||
struct eth_tx_2nd_bd second_bd;
|
||||
struct eth_tx_3rd_bd third_bd;
|
||||
struct eth_tx_bd reg_bd;
|
||||
struct eth_tx_1st_bd first_bd;
|
||||
struct eth_tx_2nd_bd second_bd;
|
||||
struct eth_tx_3rd_bd third_bd;
|
||||
struct eth_tx_bd reg_bd;
|
||||
};
|
||||
|
||||
/* Mstorm Queue Zone */
|
||||
@ -389,8 +416,8 @@ struct eth_db_data {
|
||||
#define ETH_DB_DATA_RESERVED_SHIFT 5
|
||||
#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
|
||||
#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
|
||||
u8 agg_flags;
|
||||
__le16 bd_prod;
|
||||
u8 agg_flags;
|
||||
__le16 bd_prod;
|
||||
};
|
||||
|
||||
#endif /* __ETH_COMMON__ */
|
||||
|
||||
@ -311,7 +311,7 @@ struct iscsi_login_req_hdr {
|
||||
#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
|
||||
#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
|
||||
#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
|
||||
__le32 isid_TABC;
|
||||
__le32 isid_tabc;
|
||||
__le16 tsih;
|
||||
__le16 isid_d;
|
||||
__le32 itt;
|
||||
@ -464,7 +464,7 @@ struct iscsi_login_response_hdr {
|
||||
#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
|
||||
#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
|
||||
#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
|
||||
__le32 isid_TABC;
|
||||
__le32 isid_tabc;
|
||||
__le16 tsih;
|
||||
__le16 isid_d;
|
||||
__le32 itt;
|
||||
@ -688,8 +688,7 @@ union iscsi_cqe {
|
||||
enum iscsi_cqes_type {
|
||||
ISCSI_CQE_TYPE_SOLICITED = 1,
|
||||
ISCSI_CQE_TYPE_UNSOLICITED,
|
||||
ISCSI_CQE_TYPE_SOLICITED_WITH_SENSE
|
||||
,
|
||||
ISCSI_CQE_TYPE_SOLICITED_WITH_SENSE,
|
||||
ISCSI_CQE_TYPE_TASK_CLEANUP,
|
||||
ISCSI_CQE_TYPE_DUMMY,
|
||||
MAX_ISCSI_CQES_TYPE
|
||||
@ -769,9 +768,9 @@ enum iscsi_eqe_opcode {
|
||||
ISCSI_EVENT_TYPE_UPDATE_CONN,
|
||||
ISCSI_EVENT_TYPE_CLEAR_SQ,
|
||||
ISCSI_EVENT_TYPE_TERMINATE_CONN,
|
||||
ISCSI_EVENT_TYPE_MAC_UPDATE_CONN,
|
||||
ISCSI_EVENT_TYPE_ASYN_CONNECT_COMPLETE,
|
||||
ISCSI_EVENT_TYPE_ASYN_TERMINATE_DONE,
|
||||
RESERVED8,
|
||||
RESERVED9,
|
||||
ISCSI_EVENT_TYPE_START_OF_ERROR_TYPES = 10,
|
||||
ISCSI_EVENT_TYPE_ASYN_ABORT_RCVD,
|
||||
@ -867,6 +866,7 @@ enum iscsi_ramrod_cmd_id {
|
||||
ISCSI_RAMROD_CMD_ID_UPDATE_CONN = 4,
|
||||
ISCSI_RAMROD_CMD_ID_TERMINATION_CONN = 5,
|
||||
ISCSI_RAMROD_CMD_ID_CLEAR_SQ = 6,
|
||||
ISCSI_RAMROD_CMD_ID_MAC_UPDATE = 7,
|
||||
MAX_ISCSI_RAMROD_CMD_ID
|
||||
};
|
||||
|
||||
@ -883,6 +883,16 @@ union iscsi_seq_num {
|
||||
__le16 r2t_sn;
|
||||
};
|
||||
|
||||
struct iscsi_spe_conn_mac_update {
|
||||
struct iscsi_slow_path_hdr hdr;
|
||||
__le16 conn_id;
|
||||
__le32 fw_cid;
|
||||
__le16 remote_mac_addr_lo;
|
||||
__le16 remote_mac_addr_mid;
|
||||
__le16 remote_mac_addr_hi;
|
||||
u8 reserved0[2];
|
||||
};
|
||||
|
||||
struct iscsi_spe_conn_offload {
|
||||
struct iscsi_slow_path_hdr hdr;
|
||||
__le16 conn_id;
|
||||
@ -1302,14 +1312,6 @@ struct mstorm_iscsi_stats_drv {
|
||||
struct regpair iscsi_rx_dropped_pdus_task_not_valid;
|
||||
};
|
||||
|
||||
struct ooo_opaque {
|
||||
__le32 cid;
|
||||
u8 drop_isle;
|
||||
u8 drop_size;
|
||||
u8 ooo_opcode;
|
||||
u8 ooo_isle;
|
||||
};
|
||||
|
||||
struct pstorm_iscsi_stats_drv {
|
||||
struct regpair iscsi_tx_bytes_cnt;
|
||||
struct regpair iscsi_tx_packet_cnt;
|
||||
|
||||
@ -16,19 +16,6 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/qed/common_hsi.h>
|
||||
|
||||
/* dma_addr_t manip */
|
||||
#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
|
||||
#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
|
||||
#define DMA_REGPAIR_LE(x, val) do { \
|
||||
(x).hi = DMA_HI_LE((val)); \
|
||||
(x).lo = DMA_LO_LE((val)); \
|
||||
} while (0)
|
||||
|
||||
#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
|
||||
#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64)
|
||||
#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
|
||||
#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
|
||||
|
||||
enum qed_chain_mode {
|
||||
/* Each Page contains a next pointer at its end */
|
||||
QED_CHAIN_MODE_NEXT_PTR,
|
||||
|
||||
@ -11,6 +11,14 @@
|
||||
|
||||
#define TCP_INVALID_TIMEOUT_VAL -1
|
||||
|
||||
struct ooo_opaque {
|
||||
__le32 cid;
|
||||
u8 drop_isle;
|
||||
u8 drop_size;
|
||||
u8 ooo_opcode;
|
||||
u8 ooo_isle;
|
||||
};
|
||||
|
||||
enum tcp_connect_mode {
|
||||
TCP_CONNECT_ACTIVE,
|
||||
TCP_CONNECT_PASSIVE,
|
||||
@ -18,14 +26,10 @@ enum tcp_connect_mode {
|
||||
};
|
||||
|
||||
struct tcp_init_params {
|
||||
__le32 max_cwnd;
|
||||
__le16 dup_ack_threshold;
|
||||
__le32 two_msl_timer;
|
||||
__le16 tx_sws_timer;
|
||||
__le16 min_rto;
|
||||
__le16 min_rto_rt;
|
||||
__le16 max_rto;
|
||||
u8 maxfinrt;
|
||||
u8 reserved[1];
|
||||
u8 reserved[9];
|
||||
};
|
||||
|
||||
enum tcp_ip_version {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user