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Merge branch 'am437x'
George Cherian says: ==================== The series adds CPTS support for AM4372. Patch 1 - DT changes w.r.t clock changes for AM33xx. Patch 2 - CPTS clock name harcoding in the driver is removed. Easier to pass the clock name from dt rather than hardcoding in driver. Also in prepration for DRA7x CPTS support. Patch 3 - Enable the CPTS support for both DRA7x and AM4372 in the driver. Patch 4 - Enable the Annexe F for L2 PTP for AM437x and DRA7x. Patch 5 - Change the default clocksource to dpll_core_m5 Patch 6 - DT changes for AM4372. v1 -> v2 Patch 1 and 2 Re-ordering. Seperate TS_BITS define for Hw version V2 and V3 ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
05f4640979
@ -665,6 +665,8 @@
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mac: ethernet@4a100000 {
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compatible = "ti,cpsw";
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ti,hwmods = "cpgmac0";
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clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
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clock-names = "fck", "cpts";
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cpdma_channels = <8>;
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ale_entries = <1024>;
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bd_ram_size = <0x2000>;
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@ -489,6 +489,8 @@
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#address-cells = <1>;
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#size-cells = <1>;
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ti,hwmods = "cpgmac0";
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clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
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clock-names = "fck", "cpts";
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status = "disabled";
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cpdma_channels = <8>;
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ale_entries = <1024>;
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@ -110,9 +110,25 @@ static struct ti_dt_clk am43xx_clks[] = {
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int __init am43xx_dt_clk_init(void)
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{
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struct clk *clk1, *clk2;
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ti_dt_clocks_register(am43xx_clks);
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omap2_clk_disable_autoidle_all();
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/*
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* cpsw_cpts_rft_clk has got the choice of 3 clocksources
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* dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
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* By default dpll_core_m4_ck is selected, witn this as clock
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* source the CPTS doesnot work properly. It gives clockcheck errors
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* while running PTP.
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* clockcheck: clock jumped backward or running slower than expected!
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* By selecting dpll_core_m5_ck as the clocksource fixes this issue.
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* In AM335x dpll_core_m5_ck is the default clocksource.
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*/
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clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk");
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clk2 = clk_get_sys(NULL, "dpll_core_m5_ck");
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clk_set_parent(clk1, clk2);
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return 0;
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}
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@ -248,20 +248,31 @@ struct cpsw_ss_regs {
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#define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
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#define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
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#define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
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#define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */
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#define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
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#define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
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#define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
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#define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
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#define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
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#define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
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#define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
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#define CTRL_TS_BITS \
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(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \
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TS_ANNEX_D_EN | TS_LTYPE1_EN)
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#define CTRL_V2_TS_BITS \
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(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
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TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
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#define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN)
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#define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN)
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#define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN)
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#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
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#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
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#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
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#define CTRL_V3_TS_BITS \
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(TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
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TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
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TS_LTYPE1_EN)
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#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
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#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
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#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
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/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
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#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
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@ -1376,13 +1387,27 @@ static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
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slave = &priv->slaves[priv->data.active_slave];
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ctrl = slave_read(slave, CPSW2_CONTROL);
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ctrl &= ~CTRL_ALL_TS_MASK;
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switch (priv->version) {
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case CPSW_VERSION_2:
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ctrl &= ~CTRL_V2_ALL_TS_MASK;
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if (priv->cpts->tx_enable)
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ctrl |= CTRL_TX_TS_BITS;
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if (priv->cpts->tx_enable)
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ctrl |= CTRL_V2_TX_TS_BITS;
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if (priv->cpts->rx_enable)
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ctrl |= CTRL_RX_TS_BITS;
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if (priv->cpts->rx_enable)
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ctrl |= CTRL_V2_RX_TS_BITS;
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break;
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case CPSW_VERSION_3:
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default:
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ctrl &= ~CTRL_V3_ALL_TS_MASK;
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if (priv->cpts->tx_enable)
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ctrl |= CTRL_V3_TX_TS_BITS;
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if (priv->cpts->rx_enable)
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ctrl |= CTRL_V3_RX_TS_BITS;
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break;
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}
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mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
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@ -1398,7 +1423,8 @@ static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
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struct hwtstamp_config cfg;
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if (priv->version != CPSW_VERSION_1 &&
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priv->version != CPSW_VERSION_2)
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priv->version != CPSW_VERSION_2 &&
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priv->version != CPSW_VERSION_3)
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return -EOPNOTSUPP;
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if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
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@ -1443,6 +1469,7 @@ static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
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cpsw_hwtstamp_v1(priv);
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break;
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case CPSW_VERSION_2:
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case CPSW_VERSION_3:
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cpsw_hwtstamp_v2(priv);
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break;
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default:
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@ -1459,7 +1486,8 @@ static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
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struct hwtstamp_config cfg;
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if (priv->version != CPSW_VERSION_1 &&
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priv->version != CPSW_VERSION_2)
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priv->version != CPSW_VERSION_2 &&
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priv->version != CPSW_VERSION_3)
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return -EOPNOTSUPP;
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cfg.flags = 0;
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@ -236,13 +236,11 @@ static void cpts_overflow_check(struct work_struct *work)
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schedule_delayed_work(&cpts->overflow_work, CPTS_OVERFLOW_PERIOD);
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}
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#define CPTS_REF_CLOCK_NAME "cpsw_cpts_rft_clk"
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static void cpts_clk_init(struct cpts *cpts)
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static void cpts_clk_init(struct device *dev, struct cpts *cpts)
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{
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cpts->refclk = clk_get(NULL, CPTS_REF_CLOCK_NAME);
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cpts->refclk = devm_clk_get(dev, "cpts");
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if (IS_ERR(cpts->refclk)) {
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pr_err("Failed to clk_get %s\n", CPTS_REF_CLOCK_NAME);
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dev_err(dev, "Failed to get cpts refclk\n");
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cpts->refclk = NULL;
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return;
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}
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@ -252,7 +250,6 @@ static void cpts_clk_init(struct cpts *cpts)
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static void cpts_clk_release(struct cpts *cpts)
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{
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clk_disable(cpts->refclk);
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clk_put(cpts->refclk);
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}
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static int cpts_match(struct sk_buff *skb, unsigned int ptp_class,
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@ -390,7 +387,7 @@ int cpts_register(struct device *dev, struct cpts *cpts,
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for (i = 0; i < CPTS_MAX_EVENTS; i++)
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list_add(&cpts->pool_data[i].list, &cpts->pool);
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cpts_clk_init(cpts);
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cpts_clk_init(dev, cpts);
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cpts_write32(cpts, CPTS_EN, control);
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cpts_write32(cpts, TS_PEND_EN, int_enable);
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