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net: atm: remove support for ZeitNet ZN122x ATM devices
This driver received nothing but automated fixes in the last 15 years. Since it's using virt_to_bus it's unlikely to be used on any modern platform. Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jakub Kicinski
David S. Miller
parent
5b74a20d35
commit
052e1f01bf
@ -178,7 +178,6 @@ CONFIG_NETCONSOLE=m
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CONFIG_ATM_TCP=m
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CONFIG_ATM_LANAI=m
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CONFIG_ATM_ENI=m
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CONFIG_ATM_ZATM=m
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CONFIG_ATM_NICSTAR=m
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CONFIG_ATM_IDT77252=m
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CONFIG_ATM_IA=m
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@ -255,7 +255,6 @@ CONFIG_ARCNET_COM20020_CS=m
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CONFIG_ATM_TCP=m
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CONFIG_ATM_LANAI=m
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CONFIG_ATM_ENI=m
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CONFIG_ATM_ZATM=m
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CONFIG_ATM_NICSTAR=m
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CONFIG_ATM_IDT77252=m
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CONFIG_ATM_IA=m
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@ -146,26 +146,6 @@ config ATM_ENI_BURST_RX_2W
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try this if you have disabled 4W and 8W bursts. Enabling 2W if 4W or
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8W are also set may or may not improve throughput.
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config ATM_ZATM
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tristate "ZeitNet ZN1221/ZN1225"
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depends on PCI && VIRT_TO_BUS
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help
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Driver for the ZeitNet ZN1221 (MMF) and ZN1225 (UTP-5) 155 Mbps ATM
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adapters.
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To compile this driver as a module, choose M here: the module will
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be called zatm.
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config ATM_ZATM_DEBUG
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bool "Enable extended debugging"
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depends on ATM_ZATM
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help
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Extended debugging records various events and displays that list
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when an inconsistency is detected. This mechanism is faster than
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generally using printks, but still has some impact on performance.
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Note that extended debugging may create certain race conditions
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itself. Enable this ONLY if you suspect problems with the driver.
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config ATM_NICSTAR
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tristate "IDT 77201 (NICStAR) (ForeRunnerLE)"
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depends on PCI
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@ -5,7 +5,6 @@
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fore_200e-y := fore200e.o
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obj-$(CONFIG_ATM_ZATM) += zatm.o uPD98402.o
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obj-$(CONFIG_ATM_NICSTAR) += nicstar.o
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obj-$(CONFIG_ATM_IA) += iphase.o suni.o
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obj-$(CONFIG_ATM_FORE200E) += fore_200e.o
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@ -1,293 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* drivers/atm/uPD98401.h - NEC uPD98401 (SAR) declarations */
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/* Written 1995 by Werner Almesberger, EPFL LRC */
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#ifndef DRIVERS_ATM_uPD98401_H
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#define DRIVERS_ATM_uPD98401_H
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#define MAX_CRAM_SIZE (1 << 18) /* 2^18 words */
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#define RAM_INCREMENT 1024 /* check in 4 kB increments */
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#define uPD98401_PORTS 0x24 /* probably more ? */
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/*
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* Commands
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*/
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#define uPD98401_OPEN_CHAN 0x20000000 /* open channel */
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#define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */
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#define uPD98401_CHAN_ADDR_SHIFT 3
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#define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */
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#define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */
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#define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */
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#define uPD98401_TX_READY 0x30000000 /* TX ready */
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#define uPD98401_ADD_BAT 0x34000000 /* add batches */
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#define uPD98401_POOL 0x000f0000 /* pool number */
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#define uPD98401_POOL_SHIFT 16
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#define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */
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#define uPD98401_NOP 0x3f000000 /* NOP */
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#define uPD98401_IND_ACC 0x00000000 /* Indirect Access */
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#define uPD98401_IA_RW 0x10000000 /* Read/Write (0 W, 1 R) */
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#define uPD98401_IA_B3 0x08000000 /* Byte select, 1 enable */
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#define uPD98401_IA_B2 0x04000000
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#define uPD98401_IA_B1 0x02000000
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#define uPD98401_IA_B0 0x01000000
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#define uPD98401_IA_BALL 0x0f000000 /* whole longword */
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#define uPD98401_IA_TGT 0x000c0000 /* Target */
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#define uPD98401_IA_TGT_SHIFT 18
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#define uPD98401_IA_TGT_CM 0 /* - Control Memory */
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#define uPD98401_IA_TGT_SAR 1 /* - uPD98401 registers */
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#define uPD98401_IA_TGT_PHY 3 /* - PHY device */
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#define uPD98401_IA_ADDR 0x0003ffff
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/*
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* Command Register Status
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*/
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#define uPD98401_BUSY 0x80000000 /* SAR is busy */
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#define uPD98401_LOCKED 0x40000000 /* SAR is locked by other CPU */
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/*
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* Indications
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*/
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/* Normal (AAL5) Receive Indication */
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#define uPD98401_AAL5_UINFO 0xffff0000 /* user-supplied information */
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#define uPD98401_AAL5_UINFO_SHIFT 16
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#define uPD98401_AAL5_SIZE 0x0000ffff /* PDU size (in _CELLS_ !!) */
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#define uPD98401_AAL5_CHAN 0x7fff0000 /* Channel number */
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#define uPD98401_AAL5_CHAN_SHIFT 16
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#define uPD98401_AAL5_ERR 0x00008000 /* Error indication */
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#define uPD98401_AAL5_CI 0x00004000 /* Congestion Indication */
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#define uPD98401_AAL5_CLP 0x00002000 /* CLP (>= 1 cell had CLP=1) */
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#define uPD98401_AAL5_ES 0x00000f00 /* Error Status */
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#define uPD98401_AAL5_ES_SHIFT 8
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#define uPD98401_AAL5_ES_NONE 0 /* No error */
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#define uPD98401_AAL5_ES_FREE 1 /* Receiver free buf underflow */
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#define uPD98401_AAL5_ES_FIFO 2 /* Receiver FIFO overrun */
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#define uPD98401_AAL5_ES_TOOBIG 3 /* Maximum length violation */
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#define uPD98401_AAL5_ES_CRC 4 /* CRC error */
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#define uPD98401_AAL5_ES_ABORT 5 /* User abort */
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#define uPD98401_AAL5_ES_LENGTH 6 /* Length violation */
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#define uPD98401_AAL5_ES_T1 7 /* T1 error (timeout) */
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#define uPD98401_AAL5_ES_DEACT 8 /* Deactivated with DEACT_CHAN */
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#define uPD98401_AAL5_POOL 0x0000001f /* Free buffer pool number */
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/* Raw Cell Indication */
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#define uPD98401_RAW_UINFO uPD98401_AAL5_UINFO
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#define uPD98401_RAW_UINFO_SHIFT uPD98401_AAL5_UINFO_SHIFT
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#define uPD98401_RAW_HEC 0x000000ff /* HEC */
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#define uPD98401_RAW_CHAN uPD98401_AAL5_CHAN
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#define uPD98401_RAW_CHAN_SHIFT uPD98401_AAL5_CHAN_SHIFT
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/* Transmit Indication */
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#define uPD98401_TXI_CONN 0x7fff0000 /* Connection Number */
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#define uPD98401_TXI_CONN_SHIFT 16
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#define uPD98401_TXI_ACTIVE 0x00008000 /* Channel remains active */
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#define uPD98401_TXI_PQP 0x00007fff /* Packet Queue Pointer */
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/*
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* Directly Addressable Registers
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*/
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#define uPD98401_GMR 0x00 /* General Mode Register */
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#define uPD98401_GSR 0x01 /* General Status Register */
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#define uPD98401_IMR 0x02 /* Interrupt Mask Register */
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#define uPD98401_RQU 0x03 /* Receive Queue Underrun */
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#define uPD98401_RQA 0x04 /* Receive Queue Alert */
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#define uPD98401_ADDR 0x05 /* Last Burst Address */
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#define uPD98401_VER 0x06 /* Version Number */
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#define uPD98401_SWR 0x07 /* Software Reset */
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#define uPD98401_CMR 0x08 /* Command Register */
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#define uPD98401_CMR_L 0x09 /* Command Register and Lock/Unlock */
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#define uPD98401_CER 0x0a /* Command Extension Register */
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#define uPD98401_CER_L 0x0b /* Command Ext Reg and Lock/Unlock */
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#define uPD98401_MSH(n) (0x10+(n)) /* Mailbox n Start Address High */
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#define uPD98401_MSL(n) (0x14+(n)) /* Mailbox n Start Address High */
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#define uPD98401_MBA(n) (0x18+(n)) /* Mailbox n Bottom Address */
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#define uPD98401_MTA(n) (0x1c+(n)) /* Mailbox n Tail Address */
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#define uPD98401_MWA(n) (0x20+(n)) /* Mailbox n Write Address */
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/* GMR is at 0x00 */
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#define uPD98401_GMR_ONE 0x80000000 /* Must be set to one */
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#define uPD98401_GMR_SLM 0x40000000 /* Address mode (0 word, 1 byte) */
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#define uPD98401_GMR_CPE 0x00008000 /* Control Memory Parity Enable */
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#define uPD98401_GMR_LP 0x00004000 /* Loopback */
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#define uPD98401_GMR_WA 0x00002000 /* Early Bus Write Abort/RDY */
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#define uPD98401_GMR_RA 0x00001000 /* Early Read Abort/RDY */
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#define uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */
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#define uPD98401_BURST16 0x00000800 /* 16-word burst */
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#define uPD98401_BURST8 0x00000400 /* 8-word burst */
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#define uPD98401_BURST4 0x00000200 /* 4-word burst */
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#define uPD98401_BURST2 0x00000100 /* 2-word burst */
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#define uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */
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#define uPD98401_GMR_BO 0x00000040 /* Byte Order (0 little, 1 big) */
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#define uPD98401_GMR_PM 0x00000020 /* Bus Parity Mode (0 byte, 1 word)*/
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#define uPD98401_GMR_PC 0x00000010 /* Bus Parity Control (0even,1odd) */
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#define uPD98401_GMR_BPE 0x00000008 /* Bus Parity Enable */
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#define uPD98401_GMR_DR 0x00000004 /* Receive Drop Mode (0drop,1don't)*/
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#define uPD98401_GMR_SE 0x00000002 /* Shapers Enable */
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#define uPD98401_GMR_RE 0x00000001 /* Receiver Enable */
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/* GSR is at 0x01, IMR is at 0x02 */
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#define uPD98401_INT_PI 0x80000000 /* PHY interrupt */
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#define uPD98401_INT_RQA 0x40000000 /* Receive Queue Alert */
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#define uPD98401_INT_RQU 0x20000000 /* Receive Queue Underrun */
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#define uPD98401_INT_RD 0x10000000 /* Receiver Deactivated */
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#define uPD98401_INT_SPE 0x08000000 /* System Parity Error */
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#define uPD98401_INT_CPE 0x04000000 /* Control Memory Parity Error */
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#define uPD98401_INT_SBE 0x02000000 /* System Bus Error */
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#define uPD98401_INT_IND 0x01000000 /* Initialization Done */
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#define uPD98401_INT_RCR 0x0000ff00 /* Raw Cell Received */
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#define uPD98401_INT_RCR_SHIFT 8
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#define uPD98401_INT_MF 0x000000f0 /* Mailbox Full */
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#define uPD98401_INT_MF_SHIFT 4
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#define uPD98401_INT_MM 0x0000000f /* Mailbox Modified */
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/* VER is at 0x06 */
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#define uPD98401_MAJOR 0x0000ff00 /* Major revision */
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#define uPD98401_MAJOR_SHIFT 8
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#define uPD98401_MINOR 0x000000ff /* Minor revision */
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/*
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* Indirectly Addressable Registers
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*/
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#define uPD98401_IM(n) (0x40000+(n)) /* Scheduler n I and M */
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#define uPD98401_X(n) (0x40010+(n)) /* Scheduler n X */
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#define uPD98401_Y(n) (0x40020+(n)) /* Scheduler n Y */
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#define uPD98401_PC(n) (0x40030+(n)) /* Scheduler n P, C, p and c */
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#define uPD98401_PS(n) (0x40040+(n)) /* Scheduler n priority and status */
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/* IM contents */
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#define uPD98401_IM_I 0xff000000 /* I */
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#define uPD98401_IM_I_SHIFT 24
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#define uPD98401_IM_M 0x00ffffff /* M */
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/* PC contents */
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#define uPD98401_PC_P 0xff000000 /* P */
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#define uPD98401_PC_P_SHIFT 24
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#define uPD98401_PC_C 0x00ff0000 /* C */
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#define uPD98401_PC_C_SHIFT 16
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#define uPD98401_PC_p 0x0000ff00 /* p */
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#define uPD98401_PC_p_SHIFT 8
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#define uPD98401_PC_c 0x000000ff /* c */
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/* PS contents */
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#define uPD98401_PS_PRIO 0xf0 /* Priority level (0 high, 15 low) */
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#define uPD98401_PS_PRIO_SHIFT 4
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#define uPD98401_PS_S 0x08 /* Scan - must be 0 (internal) */
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#define uPD98401_PS_R 0x04 /* Round Robin (internal) */
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#define uPD98401_PS_A 0x02 /* Active (internal) */
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#define uPD98401_PS_E 0x01 /* Enabled */
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#define uPD98401_TOS 0x40100 /* Top of Stack Control Memory Address */
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#define uPD98401_SMA 0x40200 /* Shapers Control Memory Start Address */
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#define uPD98401_PMA 0x40201 /* Receive Pool Control Memory Start Address */
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#define uPD98401_T1R 0x40300 /* T1 Register */
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#define uPD98401_VRR 0x40301 /* VPI/VCI Reduction Register/Recv. Shutdown */
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#define uPD98401_TSR 0x40302 /* Time-Stamp Register */
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/* VRR is at 0x40301 */
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#define uPD98401_VRR_SDM 0x80000000 /* Shutdown Mode */
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#define uPD98401_VRR_SHIFT 0x000f0000 /* VPI/VCI Shift */
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#define uPD98401_VRR_SHIFT_SHIFT 16
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#define uPD98401_VRR_MASK 0x0000ffff /* VPI/VCI mask */
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/*
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* TX packet descriptor
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*/
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#define uPD98401_TXPD_SIZE 16 /* descriptor size (in bytes) */
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#define uPD98401_TXPD_V 0x80000000 /* Valid bit */
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#define uPD98401_TXPD_DP 0x40000000 /* Descriptor (1) or Pointer (0) */
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#define uPD98401_TXPD_SM 0x20000000 /* Single (1) or Multiple (0) */
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#define uPD98401_TXPD_CLPM 0x18000000 /* CLP mode */
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#define uPD98401_CLPM_0 0 /* 00 CLP = 0 */
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#define uPD98401_CLPM_1 3 /* 11 CLP = 1 */
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#define uPD98401_CLPM_LAST 1 /* 01 CLP unless last cell */
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#define uPD98401_TXPD_CLPM_SHIFT 27
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#define uPD98401_TXPD_PTI 0x07000000 /* PTI pattern */
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#define uPD98401_TXPD_PTI_SHIFT 24
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#define uPD98401_TXPD_GFC 0x00f00000 /* GFC pattern */
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#define uPD98401_TXPD_GFC_SHIFT 20
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#define uPD98401_TXPD_C10 0x00040000 /* insert CRC-10 */
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#define uPD98401_TXPD_AAL5 0x00020000 /* AAL5 processing */
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#define uPD98401_TXPD_MB 0x00010000 /* TX mailbox number */
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#define uPD98401_TXPD_UU 0x0000ff00 /* CPCS-UU */
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#define uPD98401_TXPD_UU_SHIFT 8
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#define uPD98401_TXPD_CPI 0x000000ff /* CPI */
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/*
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* TX buffer descriptor
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*/
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#define uPD98401_TXBD_SIZE 8 /* descriptor size (in bytes) */
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#define uPD98401_TXBD_LAST 0x80000000 /* last buffer in packet */
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/*
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* TX VC table
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*/
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/* 1st word has the same structure as in a TX packet descriptor */
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#define uPD98401_TXVC_L 0x80000000 /* last buffer */
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#define uPD98401_TXVC_SHP 0x0f000000 /* shaper number */
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#define uPD98401_TXVC_SHP_SHIFT 24
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#define uPD98401_TXVC_VPI 0x00ff0000 /* VPI */
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#define uPD98401_TXVC_VPI_SHIFT 16
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#define uPD98401_TXVC_VCI 0x0000ffff /* VCI */
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#define uPD98401_TXVC_QRP 6 /* Queue Read Pointer is in word 6 */
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/*
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* RX free buffer pools descriptor
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*/
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#define uPD98401_RXFP_ALERT 0x70000000 /* low water mark */
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#define uPD98401_RXFP_ALERT_SHIFT 28
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#define uPD98401_RXFP_BFSZ 0x0f000000 /* buffer size, 64*2^n */
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#define uPD98401_RXFP_BFSZ_SHIFT 24
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#define uPD98401_RXFP_BTSZ 0x00ff0000 /* batch size, n+1 */
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#define uPD98401_RXFP_BTSZ_SHIFT 16
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#define uPD98401_RXFP_REMAIN 0x0000ffff /* remaining batches in pool */
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/*
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* RX VC table
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*/
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#define uPD98401_RXVC_BTSZ 0xff000000 /* remaining free buffers in batch */
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#define uPD98401_RXVC_BTSZ_SHIFT 24
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#define uPD98401_RXVC_MB 0x00200000 /* RX mailbox number */
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#define uPD98401_RXVC_POOL 0x001f0000 /* free buffer pool number */
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#define uPD98401_RXVC_POOL_SHIFT 16
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#define uPD98401_RXVC_UINFO 0x0000ffff /* user-supplied information */
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#define uPD98401_RXVC_T1 0xffff0000 /* T1 timestamp */
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#define uPD98401_RXVC_T1_SHIFT 16
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#define uPD98401_RXVC_PR 0x00008000 /* Packet Reception, 1 if busy */
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#define uPD98401_RXVC_DR 0x00004000 /* FIFO Drop */
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#define uPD98401_RXVC_OD 0x00001000 /* Drop OAM cells */
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#define uPD98401_RXVC_AR 0x00000800 /* AAL5 or raw cell; 1 if AAL5 */
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#define uPD98401_RXVC_MAXSEG 0x000007ff /* max number of segments per PDU */
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#define uPD98401_RXVC_REM 0xfffe0000 /* remaining words in curr buffer */
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#define uPD98401_RXVC_REM_SHIFT 17
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#define uPD98401_RXVC_CLP 0x00010000 /* CLP received */
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#define uPD98401_RXVC_BFA 0x00008000 /* Buffer Assigned */
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#define uPD98401_RXVC_BTA 0x00004000 /* Batch Assigned */
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#define uPD98401_RXVC_CI 0x00002000 /* Congestion Indication */
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#define uPD98401_RXVC_DD 0x00001000 /* Dropping incoming cells */
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#define uPD98401_RXVC_DP 0x00000800 /* like PR ? */
|
||||
#define uPD98401_RXVC_CURSEG 0x000007ff /* Current Segment count */
|
||||
|
||||
/*
|
||||
* RX lookup table
|
||||
*/
|
||||
|
||||
#define uPD98401_RXLT_ENBL 0x8000 /* Enable */
|
||||
|
||||
#endif
|
||||
@ -1,266 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/* drivers/atm/uPD98402.c - NEC uPD98402 (PHY) declarations */
|
||||
|
||||
/* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */
|
||||
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/atmdev.h>
|
||||
#include <linux/sonet.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/atomic.h>
|
||||
|
||||
#include "uPD98402.h"
|
||||
|
||||
|
||||
#if 0
|
||||
#define DPRINTK(format,args...) printk(KERN_DEBUG format,##args)
|
||||
#else
|
||||
#define DPRINTK(format,args...)
|
||||
#endif
|
||||
|
||||
|
||||
struct uPD98402_priv {
|
||||
struct k_sonet_stats sonet_stats;/* link diagnostics */
|
||||
unsigned char framing; /* SONET/SDH framing */
|
||||
int loop_mode; /* loopback mode */
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
|
||||
#define PRIV(dev) ((struct uPD98402_priv *) dev->phy_data)
|
||||
|
||||
#define PUT(val,reg) dev->ops->phy_put(dev,val,uPD98402_##reg)
|
||||
#define GET(reg) dev->ops->phy_get(dev,uPD98402_##reg)
|
||||
|
||||
|
||||
static int fetch_stats(struct atm_dev *dev,struct sonet_stats __user *arg,int zero)
|
||||
{
|
||||
struct sonet_stats tmp;
|
||||
int error = 0;
|
||||
|
||||
atomic_add(GET(HECCT),&PRIV(dev)->sonet_stats.uncorr_hcs);
|
||||
sonet_copy_stats(&PRIV(dev)->sonet_stats,&tmp);
|
||||
if (arg) error = copy_to_user(arg,&tmp,sizeof(tmp));
|
||||
if (zero && !error) {
|
||||
/* unused fields are reported as -1, but we must not "adjust"
|
||||
them */
|
||||
tmp.corr_hcs = tmp.tx_cells = tmp.rx_cells = 0;
|
||||
sonet_subtract_stats(&PRIV(dev)->sonet_stats,&tmp);
|
||||
}
|
||||
return error ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
|
||||
static int set_framing(struct atm_dev *dev,unsigned char framing)
|
||||
{
|
||||
static const unsigned char sonet[] = { 1,2,3,0 };
|
||||
static const unsigned char sdh[] = { 1,0,0,2 };
|
||||
const char *set;
|
||||
unsigned long flags;
|
||||
|
||||
switch (framing) {
|
||||
case SONET_FRAME_SONET:
|
||||
set = sonet;
|
||||
break;
|
||||
case SONET_FRAME_SDH:
|
||||
set = sdh;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
spin_lock_irqsave(&PRIV(dev)->lock, flags);
|
||||
PUT(set[0],C11T);
|
||||
PUT(set[1],C12T);
|
||||
PUT(set[2],C13T);
|
||||
PUT((GET(MDR) & ~uPD98402_MDR_SS_MASK) | (set[3] <<
|
||||
uPD98402_MDR_SS_SHIFT),MDR);
|
||||
spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int get_sense(struct atm_dev *dev,u8 __user *arg)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned char s[3];
|
||||
|
||||
spin_lock_irqsave(&PRIV(dev)->lock, flags);
|
||||
s[0] = GET(C11R);
|
||||
s[1] = GET(C12R);
|
||||
s[2] = GET(C13R);
|
||||
spin_unlock_irqrestore(&PRIV(dev)->lock, flags);
|
||||
return (put_user(s[0], arg) || put_user(s[1], arg+1) ||
|
||||
put_user(s[2], arg+2) || put_user(0xff, arg+3) ||
|
||||
put_user(0xff, arg+4) || put_user(0xff, arg+5)) ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
|
||||
static int set_loopback(struct atm_dev *dev,int mode)
|
||||
{
|
||||
unsigned char mode_reg;
|
||||
|
||||
mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP |
|
||||
uPD98402_MDR_RPLP);
|
||||
switch (__ATM_LM_XTLOC(mode)) {
|
||||
case __ATM_LM_NONE:
|
||||
break;
|
||||
case __ATM_LM_PHY:
|
||||
mode_reg |= uPD98402_MDR_TPLP;
|
||||
break;
|
||||
case __ATM_LM_ATM:
|
||||
mode_reg |= uPD98402_MDR_ALP;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
switch (__ATM_LM_XTRMT(mode)) {
|
||||
case __ATM_LM_NONE:
|
||||
break;
|
||||
case __ATM_LM_PHY:
|
||||
mode_reg |= uPD98402_MDR_RPLP;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
PUT(mode_reg,MDR);
|
||||
PRIV(dev)->loop_mode = mode;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int uPD98402_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
|
||||
{
|
||||
switch (cmd) {
|
||||
|
||||
case SONET_GETSTATZ:
|
||||
case SONET_GETSTAT:
|
||||
return fetch_stats(dev,arg, cmd == SONET_GETSTATZ);
|
||||
case SONET_SETFRAMING:
|
||||
return set_framing(dev, (int)(unsigned long)arg);
|
||||
case SONET_GETFRAMING:
|
||||
return put_user(PRIV(dev)->framing,(int __user *)arg) ?
|
||||
-EFAULT : 0;
|
||||
case SONET_GETFRSENSE:
|
||||
return get_sense(dev,arg);
|
||||
case ATM_SETLOOP:
|
||||
return set_loopback(dev, (int)(unsigned long)arg);
|
||||
case ATM_GETLOOP:
|
||||
return put_user(PRIV(dev)->loop_mode,(int __user *)arg) ?
|
||||
-EFAULT : 0;
|
||||
case ATM_QUERYLOOP:
|
||||
return put_user(ATM_LM_LOC_PHY | ATM_LM_LOC_ATM |
|
||||
ATM_LM_RMT_PHY,(int __user *)arg) ? -EFAULT : 0;
|
||||
default:
|
||||
return -ENOIOCTLCMD;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#define ADD_LIMITED(s,v) \
|
||||
{ atomic_add(GET(v),&PRIV(dev)->sonet_stats.s); \
|
||||
if (atomic_read(&PRIV(dev)->sonet_stats.s) < 0) \
|
||||
atomic_set(&PRIV(dev)->sonet_stats.s,INT_MAX); }
|
||||
|
||||
|
||||
static void stat_event(struct atm_dev *dev)
|
||||
{
|
||||
unsigned char events;
|
||||
|
||||
events = GET(PCR);
|
||||
if (events & uPD98402_PFM_PFEB) ADD_LIMITED(path_febe,PFECB);
|
||||
if (events & uPD98402_PFM_LFEB) ADD_LIMITED(line_febe,LECCT);
|
||||
if (events & uPD98402_PFM_B3E) ADD_LIMITED(path_bip,B3ECT);
|
||||
if (events & uPD98402_PFM_B2E) ADD_LIMITED(line_bip,B2ECT);
|
||||
if (events & uPD98402_PFM_B1E) ADD_LIMITED(section_bip,B1ECT);
|
||||
}
|
||||
|
||||
|
||||
#undef ADD_LIMITED
|
||||
|
||||
|
||||
static void uPD98402_int(struct atm_dev *dev)
|
||||
{
|
||||
static unsigned long silence = 0;
|
||||
unsigned char reason;
|
||||
|
||||
while ((reason = GET(PICR))) {
|
||||
if (reason & uPD98402_INT_LOS)
|
||||
printk(KERN_NOTICE "%s(itf %d): signal lost\n",
|
||||
dev->type,dev->number);
|
||||
if (reason & uPD98402_INT_PFM) stat_event(dev);
|
||||
if (reason & uPD98402_INT_PCO) {
|
||||
(void) GET(PCOCR); /* clear interrupt cause */
|
||||
atomic_add(GET(HECCT),
|
||||
&PRIV(dev)->sonet_stats.uncorr_hcs);
|
||||
}
|
||||
if ((reason & uPD98402_INT_RFO) &&
|
||||
(time_after(jiffies, silence) || silence == 0)) {
|
||||
printk(KERN_WARNING "%s(itf %d): uPD98402 receive "
|
||||
"FIFO overflow\n",dev->type,dev->number);
|
||||
silence = (jiffies+HZ/2)|1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static int uPD98402_start(struct atm_dev *dev)
|
||||
{
|
||||
DPRINTK("phy_start\n");
|
||||
if (!(dev->phy_data = kmalloc(sizeof(struct uPD98402_priv),GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
spin_lock_init(&PRIV(dev)->lock);
|
||||
memset(&PRIV(dev)->sonet_stats,0,sizeof(struct k_sonet_stats));
|
||||
(void) GET(PCR); /* clear performance events */
|
||||
PUT(uPD98402_PFM_FJ,PCMR); /* ignore frequency adj */
|
||||
(void) GET(PCOCR); /* clear overflows */
|
||||
PUT(~uPD98402_PCO_HECC,PCOMR);
|
||||
(void) GET(PICR); /* clear interrupts */
|
||||
PUT(~(uPD98402_INT_PFM | uPD98402_INT_ALM | uPD98402_INT_RFO |
|
||||
uPD98402_INT_LOS),PIMR); /* enable them */
|
||||
(void) fetch_stats(dev,NULL,1); /* clear kernel counters */
|
||||
atomic_set(&PRIV(dev)->sonet_stats.corr_hcs,-1);
|
||||
atomic_set(&PRIV(dev)->sonet_stats.tx_cells,-1);
|
||||
atomic_set(&PRIV(dev)->sonet_stats.rx_cells,-1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int uPD98402_stop(struct atm_dev *dev)
|
||||
{
|
||||
/* let SAR driver worry about stopping interrupts */
|
||||
kfree(PRIV(dev));
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct atmphy_ops uPD98402_ops = {
|
||||
.start = uPD98402_start,
|
||||
.ioctl = uPD98402_ioctl,
|
||||
.interrupt = uPD98402_int,
|
||||
.stop = uPD98402_stop,
|
||||
};
|
||||
|
||||
|
||||
int uPD98402_init(struct atm_dev *dev)
|
||||
{
|
||||
DPRINTK("phy_init\n");
|
||||
dev->phy = &uPD98402_ops;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
EXPORT_SYMBOL(uPD98402_init);
|
||||
|
||||
static __init int uPD98402_module_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
module_init(uPD98402_module_init);
|
||||
/* module_exit not defined so not unloadable */
|
||||
@ -1,107 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* drivers/atm/uPD98402.h - NEC uPD98402 (PHY) declarations */
|
||||
|
||||
/* Written 1995 by Werner Almesberger, EPFL LRC */
|
||||
|
||||
|
||||
#ifndef DRIVERS_ATM_uPD98402_H
|
||||
#define DRIVERS_ATM_uPD98402_H
|
||||
|
||||
/*
|
||||
* Registers
|
||||
*/
|
||||
|
||||
#define uPD98402_CMR 0x00 /* Command Register */
|
||||
#define uPD98402_MDR 0x01 /* Mode Register */
|
||||
#define uPD98402_PICR 0x02 /* PHY Interrupt Cause Register */
|
||||
#define uPD98402_PIMR 0x03 /* PHY Interrupt Mask Register */
|
||||
#define uPD98402_ACR 0x04 /* Alarm Cause Register */
|
||||
#define uPD98402_ACMR 0x05 /* Alarm Cause Mask Register */
|
||||
#define uPD98402_PCR 0x06 /* Performance Cause Register */
|
||||
#define uPD98402_PCMR 0x07 /* Performance Cause Mask Register */
|
||||
#define uPD98402_IACM 0x08 /* Internal Alarm Cause Mask Register */
|
||||
#define uPD98402_B1ECT 0x09 /* B1 Error Count Register */
|
||||
#define uPD98402_B2ECT 0x0a /* B2 Error Count Register */
|
||||
#define uPD98402_B3ECT 0x0b /* B3 Error Count Regster */
|
||||
#define uPD98402_PFECB 0x0c /* Path FEBE Count Register */
|
||||
#define uPD98402_LECCT 0x0d /* Line FEBE Count Register */
|
||||
#define uPD98402_HECCT 0x0e /* HEC Error Count Register */
|
||||
#define uPD98402_FJCT 0x0f /* Frequence Justification Count Reg */
|
||||
#define uPD98402_PCOCR 0x10 /* Perf. Counter Overflow Cause Reg */
|
||||
#define uPD98402_PCOMR 0x11 /* Perf. Counter Overflow Mask Reg */
|
||||
#define uPD98402_C11T 0x20 /* C11T Data Register */
|
||||
#define uPD98402_C12T 0x21 /* C12T Data Register */
|
||||
#define uPD98402_C13T 0x22 /* C13T Data Register */
|
||||
#define uPD98402_F1T 0x23 /* F1T Data Register */
|
||||
#define uPD98402_K2T 0x25 /* K2T Data Register */
|
||||
#define uPD98402_C2T 0x26 /* C2T Data Register */
|
||||
#define uPD98402_F2T 0x27 /* F2T Data Register */
|
||||
#define uPD98402_C11R 0x30 /* C11T Data Register */
|
||||
#define uPD98402_C12R 0x31 /* C12T Data Register */
|
||||
#define uPD98402_C13R 0x32 /* C13T Data Register */
|
||||
#define uPD98402_F1R 0x33 /* F1T Data Register */
|
||||
#define uPD98402_K2R 0x35 /* K2T Data Register */
|
||||
#define uPD98402_C2R 0x36 /* C2T Data Register */
|
||||
#define uPD98402_F2R 0x37 /* F2T Data Register */
|
||||
|
||||
/* CMR is at 0x00 */
|
||||
#define uPD98402_CMR_PFRF 0x01 /* Send path FERF */
|
||||
#define uPD98402_CMR_LFRF 0x02 /* Send line FERF */
|
||||
#define uPD98402_CMR_PAIS 0x04 /* Send path AIS */
|
||||
#define uPD98402_CMR_LAIS 0x08 /* Send line AIS */
|
||||
|
||||
/* MDR is at 0x01 */
|
||||
#define uPD98402_MDR_ALP 0x01 /* ATM layer loopback */
|
||||
#define uPD98402_MDR_TPLP 0x02 /* PMD loopback, to host */
|
||||
#define uPD98402_MDR_RPLP 0x04 /* PMD loopback, to network */
|
||||
#define uPD98402_MDR_SS0 0x08 /* SS0 */
|
||||
#define uPD98402_MDR_SS1 0x10 /* SS1 */
|
||||
#define uPD98402_MDR_SS_MASK 0x18 /* mask */
|
||||
#define uPD98402_MDR_SS_SHIFT 3 /* shift */
|
||||
#define uPD98402_MDR_HEC 0x20 /* disable HEC inbound processing */
|
||||
#define uPD98402_MDR_FSR 0x40 /* disable frame scrambler */
|
||||
#define uPD98402_MDR_CSR 0x80 /* disable cell scrambler */
|
||||
|
||||
/* PICR is at 0x02, PIMR is at 0x03 */
|
||||
#define uPD98402_INT_PFM 0x01 /* performance counter has changed */
|
||||
#define uPD98402_INT_ALM 0x02 /* line fault */
|
||||
#define uPD98402_INT_RFO 0x04 /* receive FIFO overflow */
|
||||
#define uPD98402_INT_PCO 0x08 /* performance counter overflow */
|
||||
#define uPD98402_INT_OTD 0x20 /* OTD has occurred */
|
||||
#define uPD98402_INT_LOS 0x40 /* Loss Of Signal */
|
||||
#define uPD98402_INT_LOF 0x80 /* Loss Of Frame */
|
||||
|
||||
/* ACR is as 0x04, ACMR is at 0x05 */
|
||||
#define uPD98402_ALM_PFRF 0x01 /* path FERF */
|
||||
#define uPD98402_ALM_LFRF 0x02 /* line FERF */
|
||||
#define uPD98402_ALM_PAIS 0x04 /* path AIS */
|
||||
#define uPD98402_ALM_LAIS 0x08 /* line AIS */
|
||||
#define uPD98402_ALM_LOD 0x10 /* loss of delineation */
|
||||
#define uPD98402_ALM_LOP 0x20 /* loss of pointer */
|
||||
#define uPD98402_ALM_OOF 0x40 /* out of frame */
|
||||
|
||||
/* PCR is at 0x06, PCMR is at 0x07 */
|
||||
#define uPD98402_PFM_PFEB 0x01 /* path FEBE */
|
||||
#define uPD98402_PFM_LFEB 0x02 /* line FEBE */
|
||||
#define uPD98402_PFM_B3E 0x04 /* B3 error */
|
||||
#define uPD98402_PFM_B2E 0x08 /* B2 error */
|
||||
#define uPD98402_PFM_B1E 0x10 /* B1 error */
|
||||
#define uPD98402_PFM_FJ 0x20 /* frequency justification */
|
||||
|
||||
/* IACM is at 0x08 */
|
||||
#define uPD98402_IACM_PFRF 0x01 /* don't generate path FERF */
|
||||
#define uPD98402_IACM_LFRF 0x02 /* don't generate line FERF */
|
||||
|
||||
/* PCOCR is at 0x010, PCOMR is at 0x11 */
|
||||
#define uPD98402_PCO_B1EC 0x01 /* B1ECT overflow */
|
||||
#define uPD98402_PCO_B2EC 0x02 /* B2ECT overflow */
|
||||
#define uPD98402_PCO_B3EC 0x04 /* B3ECT overflow */
|
||||
#define uPD98402_PCO_PFBC 0x08 /* PFEBC overflow */
|
||||
#define uPD98402_PCO_LFBC 0x10 /* LFEVC overflow */
|
||||
#define uPD98402_PCO_HECC 0x20 /* HECCT overflow */
|
||||
#define uPD98402_PCO_FJC 0x40 /* FJCT overflow */
|
||||
|
||||
|
||||
int uPD98402_init(struct atm_dev *dev);
|
||||
|
||||
#endif
|
||||
1652
drivers/atm/zatm.c
1652
drivers/atm/zatm.c
File diff suppressed because it is too large
Load Diff
@ -1,104 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* drivers/atm/zatm.h - ZeitNet ZN122x device driver declarations */
|
||||
|
||||
/* Written 1995-1998 by Werner Almesberger, EPFL LRC/ICA */
|
||||
|
||||
|
||||
#ifndef DRIVER_ATM_ZATM_H
|
||||
#define DRIVER_ATM_ZATM_H
|
||||
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/atm.h>
|
||||
#include <linux/atmdev.h>
|
||||
#include <linux/sonet.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
|
||||
#define DEV_LABEL "zatm"
|
||||
|
||||
#define MAX_AAL5_PDU 10240 /* allocate for AAL5 PDUs of this size */
|
||||
#define MAX_RX_SIZE_LD 14 /* ceil(log2((MAX_AAL5_PDU+47)/48)) */
|
||||
|
||||
#define LOW_MARK 12 /* start adding new buffers if less than 12 */
|
||||
#define HIGH_MARK 30 /* stop adding buffers after reaching 30 */
|
||||
#define OFF_CNG_THRES 5 /* threshold for offset changes */
|
||||
|
||||
#define RX_SIZE 2 /* RX lookup entry size (in bytes) */
|
||||
#define NR_POOLS 32 /* number of free buffer pointers */
|
||||
#define POOL_SIZE 8 /* buffer entry size (in bytes) */
|
||||
#define NR_SHAPERS 16 /* number of shapers */
|
||||
#define SHAPER_SIZE 4 /* shaper entry size (in bytes) */
|
||||
#define VC_SIZE 32 /* VC dsc (TX or RX) size (in bytes) */
|
||||
|
||||
#define RING_ENTRIES 32 /* ring entries (without back pointer) */
|
||||
#define RING_WORDS 4 /* ring element size */
|
||||
#define RING_SIZE (sizeof(unsigned long)*(RING_ENTRIES+1)*RING_WORDS)
|
||||
|
||||
#define NR_MBX 4 /* four mailboxes */
|
||||
#define MBX_RX_0 0 /* mailbox indices */
|
||||
#define MBX_RX_1 1
|
||||
#define MBX_TX_0 2
|
||||
#define MBX_TX_1 3
|
||||
|
||||
struct zatm_vcc {
|
||||
/*-------------------------------- RX part */
|
||||
int rx_chan; /* RX channel, 0 if none */
|
||||
int pool; /* free buffer pool */
|
||||
/*-------------------------------- TX part */
|
||||
int tx_chan; /* TX channel, 0 if none */
|
||||
int shaper; /* shaper, <0 if none */
|
||||
struct sk_buff_head tx_queue; /* list of buffers in transit */
|
||||
wait_queue_head_t tx_wait; /* for close */
|
||||
u32 *ring; /* transmit ring */
|
||||
int ring_curr; /* current write position */
|
||||
int txing; /* number of transmits in progress */
|
||||
struct sk_buff_head backlog; /* list of buffers waiting for ring */
|
||||
};
|
||||
|
||||
struct zatm_dev {
|
||||
/*-------------------------------- TX part */
|
||||
int tx_bw; /* remaining bandwidth */
|
||||
u32 free_shapers; /* bit set */
|
||||
int ubr; /* UBR shaper; -1 if none */
|
||||
int ubr_ref_cnt; /* number of VCs using UBR shaper */
|
||||
/*-------------------------------- RX part */
|
||||
int pool_ref[NR_POOLS]; /* free buffer pool usage counters */
|
||||
volatile struct sk_buff *last_free[NR_POOLS];
|
||||
/* last entry in respective pool */
|
||||
struct sk_buff_head pool[NR_POOLS];/* free buffer pools */
|
||||
struct zatm_pool_info pool_info[NR_POOLS]; /* pool information */
|
||||
/*-------------------------------- maps */
|
||||
struct atm_vcc **tx_map; /* TX VCCs */
|
||||
struct atm_vcc **rx_map; /* RX VCCs */
|
||||
int chans; /* map size, must be 2^n */
|
||||
/*-------------------------------- mailboxes */
|
||||
unsigned long mbx_start[NR_MBX];/* start addresses */
|
||||
dma_addr_t mbx_dma[NR_MBX];
|
||||
u16 mbx_end[NR_MBX]; /* end offset (in bytes) */
|
||||
/*-------------------------------- other pointers */
|
||||
u32 pool_base; /* Free buffer pool dsc (word addr) */
|
||||
/*-------------------------------- ZATM links */
|
||||
struct atm_dev *more; /* other ZATM devices */
|
||||
/*-------------------------------- general information */
|
||||
int mem; /* RAM on board (in bytes) */
|
||||
int khz; /* timer clock */
|
||||
int copper; /* PHY type */
|
||||
unsigned char irq; /* IRQ */
|
||||
unsigned int base; /* IO base address */
|
||||
struct pci_dev *pci_dev; /* PCI stuff */
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
|
||||
#define ZATM_DEV(d) ((struct zatm_dev *) (d)->dev_data)
|
||||
#define ZATM_VCC(d) ((struct zatm_vcc *) (d)->dev_data)
|
||||
|
||||
|
||||
struct zatm_skb_prv {
|
||||
struct atm_skb_data _; /* reserved */
|
||||
u32 *dsc; /* pointer to skb's descriptor */
|
||||
};
|
||||
|
||||
#define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
|
||||
|
||||
#endif
|
||||
@ -1,47 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
/* atm_zatm.h - Driver-specific declarations of the ZATM driver (for use by
|
||||
driver-specific utilities) */
|
||||
|
||||
/* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
|
||||
|
||||
|
||||
#ifndef LINUX_ATM_ZATM_H
|
||||
#define LINUX_ATM_ZATM_H
|
||||
|
||||
/*
|
||||
* Note: non-kernel programs including this file must also include
|
||||
* sys/types.h for struct timeval
|
||||
*/
|
||||
|
||||
#include <linux/atmapi.h>
|
||||
#include <linux/atmioc.h>
|
||||
|
||||
#define ZATM_GETPOOL _IOW('a',ATMIOC_SARPRV+1,struct atmif_sioc)
|
||||
/* get pool statistics */
|
||||
#define ZATM_GETPOOLZ _IOW('a',ATMIOC_SARPRV+2,struct atmif_sioc)
|
||||
/* get statistics and zero */
|
||||
#define ZATM_SETPOOL _IOW('a',ATMIOC_SARPRV+3,struct atmif_sioc)
|
||||
/* set pool parameters */
|
||||
|
||||
struct zatm_pool_info {
|
||||
int ref_count; /* free buffer pool usage counters */
|
||||
int low_water,high_water; /* refill parameters */
|
||||
int rqa_count,rqu_count; /* queue condition counters */
|
||||
int offset,next_off; /* alignment optimizations: offset */
|
||||
int next_cnt,next_thres; /* repetition counter and threshold */
|
||||
};
|
||||
|
||||
struct zatm_pool_req {
|
||||
int pool_num; /* pool number */
|
||||
struct zatm_pool_info info; /* actual information */
|
||||
};
|
||||
|
||||
#define ZATM_OAM_POOL 0 /* free buffer pool for OAM cells */
|
||||
#define ZATM_AAL0_POOL 1 /* free buffer pool for AAL0 cells */
|
||||
#define ZATM_AAL5_POOL_BASE 2 /* first AAL5 free buffer pool */
|
||||
#define ZATM_LAST_POOL ZATM_AAL5_POOL_BASE+10 /* max. 64 kB */
|
||||
|
||||
#define ZATM_TIMER_HISTORY_SIZE 16 /* number of timer adjustments to
|
||||
record; must be 2^n */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user