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bnx2x: Using registers name
Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Eilon Greenstein
David S. Miller
parent
c2c8b03e20
commit
052a38e096
@ -446,10 +446,13 @@ struct bnx2x_fastpath {
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#define BNX2X_RX_CSUM_OK(cqe) \
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(!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
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#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
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(((le16_to_cpu(flags) & \
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PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
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PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
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== PRS_FLAG_OVERETH_IPV4)
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#define BNX2X_RX_SUM_FIX(cqe) \
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((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \
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PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
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(1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
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BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
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#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
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@ -2094,7 +2094,7 @@ static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc801, &val);
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MDIO_PMA_REG_8073_CHIP_REV, &val);
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if (val != 1) {
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/* No need to workaround in 8073 A1 */
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@ -2126,7 +2126,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc801, &val);
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MDIO_PMA_REG_8073_CHIP_REV, &val);
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if (val > 0) {
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/* No need to workaround in 8073 A1 */
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@ -2142,7 +2142,8 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc820, &val);
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MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
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&val);
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/* If bit [14] = 0 or bit [13] = 0, continue on with
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system initialization (XAUI work-around not required,
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as these bits indicate 2.5G or 1G link up). */
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@ -2160,7 +2161,7 @@ static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc841, &val);
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MDIO_PMA_REG_8073_XAUI_WA, &val);
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if (val & (1<<15)) {
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DP(NETIF_MSG_LINK,
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"XAUI workaround has completed\n");
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@ -2758,7 +2759,7 @@ static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc801, &val);
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MDIO_PMA_REG_8073_CHIP_REV, &val);
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if (val == 0) {
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/* Mustn't set low power mode in 8073 A0 */
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@ -3283,7 +3284,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xca13,
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MDIO_PMA_REG_M8051_MSGOUT_REG,
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&tmp1);
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bnx2x_cl45_read(bp, params->port,
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@ -3350,7 +3351,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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0x8329, &tmp1);
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MDIO_AN_REG_8073_2_5G, &tmp1);
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if (((params->speed_cap_mask &
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PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
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@ -3364,7 +3365,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc801, &phy_ver);
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MDIO_PMA_REG_8073_CHIP_REV, &phy_ver);
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DP(NETIF_MSG_LINK, "Add 2.5G\n");
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if (phy_ver > 0)
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tmp1 |= 1;
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@ -3379,7 +3380,7 @@ static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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0x8329, tmp1);
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MDIO_AN_REG_8073_2_5G, tmp1);
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}
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/* Add support for CL37 (passive mode) II */
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@ -3737,7 +3738,7 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xca13,
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MDIO_PMA_REG_M8051_MSGOUT_REG,
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&val1);
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/* Check the LASI */
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@ -3782,17 +3783,17 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
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}
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}
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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0x8304,
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&an1000_status);
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_LINK_STATUS,
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&an1000_status);
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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0x8304,
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&an1000_status);
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_LINK_STATUS,
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&an1000_status);
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/* Check the link status on 1.1.2 */
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bnx2x_cl45_read(bp, params->port,
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@ -3837,11 +3838,11 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
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}
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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0xc820,
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&link_status);
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ext_phy_type,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
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&link_status);
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/* Bits 0..2 --> speed detected,
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bits 13..15--> link is down */
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@ -3875,17 +3876,17 @@ static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
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} else {
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/* See if 1G link is up for the 8072 */
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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0x8304,
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&an1000_status);
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_LINK_STATUS,
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&an1000_status);
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bnx2x_cl45_read(bp, params->port,
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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0x8304,
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&an1000_status);
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ext_phy_type,
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ext_phy_addr,
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MDIO_AN_DEVAD,
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MDIO_AN_REG_LINK_STATUS,
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&an1000_status);
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if (an1000_status & (1<<1)) {
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ext_phy_link_up = 1;
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vars->line_speed = SPEED_1000;
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@ -5239,6 +5239,7 @@
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#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
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#define HW_LOCK_RESOURCE_SPIO 2
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#define HW_LOCK_RESOURCE_UNDI 5
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#define PRS_FLAG_OVERETH_IPV4 1
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#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
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#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
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#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
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@ -5861,6 +5862,10 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
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#define MDIO_PMA_REG_8073_CHIP_REV 0xc801
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#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
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#define MDIO_PMA_REG_8073_XAUI_WA 0xc841
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#define MDIO_PMA_REG_7101_RESET 0xc000
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#define MDIO_PMA_REG_7107_LED_CNTL 0xc007
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#define MDIO_PMA_REG_7101_VER1 0xc026
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@ -5917,6 +5922,8 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_AN_REG_CL37_FC_LD 0xffe4
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#define MDIO_AN_REG_CL37_FC_LP 0xffe5
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#define MDIO_AN_REG_8073_2_5G 0x8329
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#define IGU_FUNC_BASE 0x0400
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