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arm/arm64: dts: arm: Use generic clock and regulator nodenames

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With the recent defining of preferred naming for fixed clock and
regulator nodes, convert the Arm Ltd. boards to use the preferred
names. In the cases which had a unit-address, warnings about missing
"reg" property are fixed.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Link: https://lore.kernel.org/20240528191536.1444649-2-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240630-arm-dts-fixes-2-v1-1-a32ba57e5b1d@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Rob Herring (Arm) 2024-06-30 00:15:35 +02:00 committed by Arnd Bergmann
parent 7f8165eee1
commit 04f08ef291
No known key found for this signature in database
GPG Key ID: 60AB47FFC9095227
23 changed files with 104 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi
View File

@ -22,7 +22,7 @@
/ {
/* Introduce a fixed regulator for the new ethernet controller */
veth: fixedregulator@0 {
veth: regulator-veth {
compatible = "regulator-fixed";
regulator-name = "veth";
regulator-min-microvolt = <3300000>;

6
arch/arm/boot/dts/arm/arm-realview-eb.dtsi
View File

@ -45,7 +45,7 @@
};
/* The voltage to the MMC card is hardwired at 3.3V */
vmmc: fixedregulator@0 {
vmmc: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
@ -59,7 +59,7 @@
clock-frequency = <24000000>;
};
timclk: timclk@1M {
timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@ -68,7 +68,7 @@
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;

4
arch/arm/boot/dts/arm/arm-realview-pb1176.dts
View File

@ -69,7 +69,7 @@
clock-frequency = <24000000>;
};
timclk: timclk@1M {
timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@ -78,7 +78,7 @@
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;

6
arch/arm/boot/dts/arm/arm-realview-pb11mp.dts
View File

@ -169,13 +169,13 @@
clock-frequency = <24000000>;
};
refclk32khz: refclk32khz {
refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
timclk: timclk@1M {
timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@ -184,7 +184,7 @@
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;

6
arch/arm/boot/dts/arm/arm-realview-pbx.dtsi
View File

@ -68,13 +68,13 @@
clock-frequency = <24000000>;
};
refclk32khz: refclk32khz {
refclk32khz: clock-32768 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
timclk: timclk@1M {
timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@ -83,7 +83,7 @@
};
/* FIXME: this actually hangs off the PLL clocks */
pclk: pclk@0 {
pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;

4
arch/arm/boot/dts/arm/integratorap-im-pd1.dts
View File

@ -54,7 +54,7 @@
};
/* Also used for the Smart Card Interface SCI */
impd1_uartclk: clock@1_4 {
impd1_uartclk: clock-uart {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <4>;
@ -64,7 +64,7 @@
};
/* For the SSP the clock is divided by 64 */
impd1_sspclk: clock@1_64 {
impd1_sspclk: clock-ssp {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
clock-div = <64>;

4
arch/arm/boot/dts/arm/integratorap.dts
View File

@ -64,7 +64,7 @@
};
/* The UART clock is 14.74 MHz divided by an ICS525 */
uartclk: uartclk@14.74M {
uartclk: clock-14745600 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
@ -73,7 +73,7 @@
core-module@10000000 {
/* 24 MHz chrystal on the core module */
cm24mhz: cm24mhz@24M {
cm24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;

14
arch/arm/boot/dts/arm/integratorcp.dts
View File

@ -47,14 +47,14 @@
*/
/* The codec chrystal operates at 24.576 MHz */
xtal_codec: xtal24.576@24.576M {
xtal_codec: clock-24576000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24576000>;
};
/* The chrystal is divided by 2 by the codec for the AACI bit clock */
aaci_bitclk: aaci_bitclk@12.288M {
aaci_bitclk: clock-12288000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <2>;
@ -63,21 +63,21 @@
};
/* This is a 25MHz chrystal on the base board */
xtal25mhz: xtal25mhz@25M {
xtal25mhz: clock-25000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <25000000>;
};
/* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
uartclk: uartclk@14.74M {
uartclk: clock-14745600 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <14745600>;
};
/* Actually sysclk I think */
pclk: pclk@0 {
pclk: clock-pclk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
@ -85,7 +85,7 @@
core-module@10000000 {
/* 24 MHz chrystal on the core module */
cm24mhz: cm24mhz@24M {
cm24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@ -131,7 +131,7 @@
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
timclk: timclk@1M {
timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;

14
arch/arm/boot/dts/arm/mps2.dtsi
View File

@ -48,31 +48,31 @@
#address-cells = <1>;
#size-cells = <1>;
oscclk0: clk-osc0 {
oscclk0: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
oscclk1: clk-osc1 {
oscclk1: clock-24576000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
};
oscclk2: clk-osc2 {
oscclk2: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: clk-cfg {
cfgclk: clock-5000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <5000000>;
};
spicfgclk: clk-spicfg {
spicfgclk: clock-75000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <75000000>;
@ -86,7 +86,7 @@
clock-mult = <1>;
};
audmclk: clk-audm {
audmclk: clk-12388000 {
compatible = "fixed-factor-clock";
clocks = <&oscclk1>;
#clock-cells = <0>;
@ -94,7 +94,7 @@
clock-mult = <1>;
};
audsclk: clk-auds {
audsclk: clk-3072000 {
compatible = "fixed-factor-clock";
clocks = <&oscclk1>;
#clock-cells = <0>;

8
arch/arm/boot/dts/arm/versatile-ab.dts
View File

@ -24,7 +24,7 @@
reg = <0x0 0x08000000>;
};
xtal24mhz: xtal24mhz@24M {
xtal24mhz: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
@ -142,14 +142,14 @@
};
/* OSC1 on AB, OSC4 on PB */
osc1: cm_aux_osc@24M {
osc1: clock-osc {
#clock-cells = <0>;
compatible = "arm,versatile-cm-auxosc";
clocks = <&xtal24mhz>;
};
/* The timer clock is the 24 MHz oscillator divided to 1MHz */
timclk: timclk@1M {
timclk: clock-1000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <24>;
@ -157,7 +157,7 @@
clocks = <&xtal24mhz>;
};
pclk: pclk@24M {
pclk: clock-24000000 {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clock-div = <1>;

8
arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi
View File

@ -20,7 +20,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
v2m_fixed_3v3: fixed-regulator-0 {
v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
@ -28,21 +28,21 @@
regulator-always-on;
};
v2m_clk24mhz: clk24mhz {
v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;

16
arch/arm/boot/dts/arm/vexpress-v2m.dtsi
View File

@ -351,7 +351,7 @@
};
};
v2m_fixed_3v3: fixed-regulator-0 {
v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
@ -359,21 +359,21 @@
regulator-always-on;
};
v2m_clk24mhz: clk24mhz {
v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
@ -436,7 +436,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0 {
clock-controller-0 {
/* MCC static memory clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@ -445,7 +445,7 @@
clock-output-names = "v2m:oscclk0";
};
v2m_oscclk1: oscclk1 {
v2m_oscclk1: clock-controller-1 {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@ -454,7 +454,7 @@
clock-output-names = "v2m:oscclk1";
};
v2m_oscclk2: oscclk2 {
v2m_oscclk2: clock-controller-2 {
/* IO FPGA peripheral clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@ -463,7 +463,7 @@
clock-output-names = "v2m:oscclk2";
};
volt-vio {
regulator-vio {
/* Logic level voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;

14
arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts
View File

@ -142,7 +142,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0 {
clock-controller-0 {
/* CPU PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@ -151,7 +151,7 @@
clock-output-names = "oscclk0";
};
oscclk4 {
clock-controller-4 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@ -160,7 +160,7 @@
clock-output-names = "oscclk4";
};
hdlcd_clk: oscclk5 {
hdlcd_clk: clock-controller-5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
@ -169,7 +169,7 @@
clock-output-names = "oscclk5";
};
smbclk: oscclk6 {
smbclk: clock-controller-6 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
@ -178,7 +178,7 @@
clock-output-names = "oscclk6";
};
sys_pll: oscclk7 {
sys_pll: clock-controller-7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
@ -187,7 +187,7 @@
clock-output-names = "oscclk7";
};
oscclk8 {
clock-controller-8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
@ -196,7 +196,7 @@
clock-output-names = "oscclk8";
};
volt-cores {
regulator-cores {
/* CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;

22
arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts
View File

@ -253,7 +253,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0 {
clock-controller-0 {
/* A15 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@ -262,7 +262,7 @@
clock-output-names = "oscclk0";
};
oscclk1 {
clock-controller-1 {
/* A15 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@ -271,7 +271,7 @@
clock-output-names = "oscclk1";
};
oscclk2 {
clock-controller-2 {
/* A7 PLL 0 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@ -280,7 +280,7 @@
clock-output-names = "oscclk2";
};
oscclk3 {
clock-controller-3 {
/* A7 PLL 1 reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
@ -289,7 +289,7 @@
clock-output-names = "oscclk3";
};
oscclk4 {
clock-controller-4 {
/* External AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@ -298,7 +298,7 @@
clock-output-names = "oscclk4";
};
hdlcd_clk: oscclk5 {
hdlcd_clk: clock-controller-5 {
/* HDLCD PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;
@ -307,7 +307,7 @@
clock-output-names = "oscclk5";
};
smbclk: oscclk6 {
smbclk: clock-controller-6 {
/* Static memory controller clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 6>;
@ -316,7 +316,7 @@
clock-output-names = "oscclk6";
};
oscclk7 {
clock-controller-7 {
/* SYS PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 7>;
@ -325,7 +325,7 @@
clock-output-names = "oscclk7";
};
oscclk8 {
clock-controller-8 {
/* DDR2 PLL reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 8>;
@ -334,7 +334,7 @@
clock-output-names = "oscclk8";
};
volt-a15 {
regulator-a15 {
/* A15 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
@ -345,7 +345,7 @@
label = "A15 Vcore";
};
volt-a7 {
regulator-a7 {
/* A7 CPU core voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;

12
arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts
View File

@ -145,7 +145,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
cpu_clk: oscclk0 {
cpu_clk: clock-controller-0 {
/* CPU and internal AXI reference clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@ -154,7 +154,7 @@
clock-output-names = "oscclk0";
};
axi_clk: oscclk1 {
axi_clk: clock-controller-1 {
/* Multiplexed AXI master clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@ -163,7 +163,7 @@
clock-output-names = "oscclk1";
};
oscclk2 {
clock-controller-2 {
/* DDR2 */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@ -172,7 +172,7 @@
clock-output-names = "oscclk2";
};
hdlcd_clk: oscclk3 {
hdlcd_clk: clock-controller-3 {
/* HDLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 3>;
@ -181,7 +181,7 @@
clock-output-names = "oscclk3";
};
oscclk4 {
clock-controller-4 {
/* Test chip gate configuration */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@ -190,7 +190,7 @@
clock-output-names = "oscclk4";
};
smbclk: oscclk5 {
smbclk: clock-controller-5 {
/* SMB clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 5>;

18
arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts
View File

@ -187,7 +187,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
oscclk0: extsaxiclk {
oscclk0: clock-controller-0 {
/* ACLK clock to the AXI master port on the test chip */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 0>;
@ -196,7 +196,7 @@
clock-output-names = "extsaxiclk";
};
oscclk1: clcdclk {
oscclk1: clock-controller-1 {
/* Reference clock for the CLCD */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;
@ -205,7 +205,7 @@
clock-output-names = "clcdclk";
};
smbclk: oscclk2: tcrefclk {
smbclk: oscclk2: clock-controller-2 {
/* Reference clock for the test chip internal PLLs */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 2>;
@ -214,7 +214,7 @@
clock-output-names = "tcrefclk";
};
volt-vd10 {
regulator-vd10 {
/* Test Chip internal logic voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
@ -223,7 +223,7 @@
label = "VD10";
};
volt-vd10-s2 {
regulator-vd10-s2 {
/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;
@ -232,7 +232,7 @@
label = "VD10_S2";
};
volt-vd10-s3 {
regulator-vd10-s3 {
/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 2>;
@ -241,7 +241,7 @@
label = "VD10_S3";
};
volt-vcc1v8 {
regulator-vcc1v8 {
/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 3>;
@ -250,7 +250,7 @@
label = "VCC1V8";
};
volt-ddr2vtt {
regulator-ddr2vtt {
/* DDR2 SDRAM VTT termination voltage */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 4>;
@ -259,7 +259,7 @@
label = "DDR2VTT";
};
volt-vcc3v3 {
regulator-vcc3v3 {
/* Local board supply for miscellaneous logic external to the Test Chip */
arm,vexpress-sysreg,func = <2 5>;
compatible = "arm,vexpress-volt";

2
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
View File

@ -21,7 +21,7 @@
reg-io-width = <2>;
};
vmmc_v3_3d: fixed_v3_3d {
vmmc_v3_3d: regulator-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc_supply";
regulator-min-microvolt = <3300000>;

6
arch/arm64/boot/dts/arm/corstone1000.dtsi
View File

@ -60,14 +60,14 @@
cache-sets = <1024>;
};
refclk100mhz: refclk100mhz {
refclk100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
smbclk: refclk24mhzx2 {
smbclk: clock-48000000 {
/* Reference 24MHz clock x 2 */
compatible = "fixed-clock";
#clock-cells = <0>;
@ -83,7 +83,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
uartclk: uartclk {
uartclk: clock-50000000 {
/* UART clock - 50MHz */
compatible = "fixed-clock";
#clock-cells = <0>;

6
arch/arm64/boot/dts/arm/foundation-v8.dtsi
View File

@ -99,21 +99,21 @@
timeout-sec = <30>;
};
v2m_clk24mhz: clk24mhz {
v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;

10
arch/arm64/boot/dts/arm/juno-clocks.dtsi
View File

@ -8,35 +8,35 @@
*/
/ {
/* SoC fixed clocks */
soc_uartclk: refclk7372800hz {
soc_uartclk: clock-7372800 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <7372800>;
clock-output-names = "juno:uartclk";
};
soc_usb48mhz: clk48mhz {
soc_usb48mhz: clock-48000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
clock-output-names = "clk48mhz";
};
soc_smc50mhz: clk50mhz {
soc_smc50mhz: clock-50000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "smc_clk";
};
soc_refclk100mhz: refclk100mhz {
soc_refclk100mhz: clock-100000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
soc_faxiclk: refclk400mhz {
soc_faxiclk: clock-400000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;

10
arch/arm64/boot/dts/arm/juno-motherboard.dtsi
View File

@ -8,35 +8,35 @@
*/
/ {
mb_clk24mhz: clk24mhz {
mb_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "juno_mb:clk24mhz";
};
mb_clk25mhz: clk25mhz {
mb_clk25mhz: clock-25000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "juno_mb:clk25mhz";
};
v2m_refclk1mhz: refclk1mhz {
v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "juno_mb:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "juno_mb:refclk32khz";
};
mb_fixed_3v3: mcc-sb-3v3 {
mb_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "MCC_SB_3V3";
regulator-min-microvolt = <3300000>;

10
arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi
View File

@ -8,28 +8,28 @@
* VEMotherBoard.lisa
*/
/ {
v2m_clk24mhz: clk24mhz {
v2m_clk24mhz: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
v2m_refclk1mhz: clock-1000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
v2m_refclk32khz: clock-32768 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
v2m_fixed_3v3: v2m-3v3 {
v2m_fixed_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3V3";
regulator-min-microvolt = <3300000>;
@ -41,7 +41,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
v2m_oscclk1: oscclk1 {
v2m_oscclk1: clock-controller {
/* CLCD clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 1>;

6
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View File

@ -111,7 +111,7 @@
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
smbclk: smclk {
smbclk: clock-controller {
/* SMC clock */
compatible = "arm,vexpress-osc";
arm,vexpress-sysreg,func = <1 4>;
@ -120,7 +120,7 @@
clock-output-names = "smclk";
};
volt-vio {
regulator-vio {
/* VIO to expansion board above */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
@ -130,7 +130,7 @@
regulator-always-on;
};
volt-12v {
regulator-12v {
/* 12V from power connector J6 */
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 1>;