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iio: trigger: stm32-timer-trigger: make use of regmap_clear_bits(), regmap_set_bits()

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Instead of using regmap_update_bits() and passing the mask twice, use
regmap_set_bits().

Instead of using regmap_update_bits() and passing val = 0, use
regmap_clear_bits().

Suggested-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Trevor Gamblin <tgamblin@baylibre.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://patch.msgid.link/20240617-review-v3-41-88d1338c4cca@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Trevor Gamblin 2024-06-17 09:50:21 -04:00 committed by Jonathan Cameron
parent ac403e8ca2
commit 04eb94997e
1 changed files with 16 additions and 18 deletions
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34
drivers/iio/trigger/stm32-timer-trigger.c
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@ -158,7 +158,7 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,
regmap_write(priv->regmap, TIM_PSC, prescaler);
regmap_write(priv->regmap, TIM_ARR, prd - 1);
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
/* Force master mode to update mode */
if (stm32_timer_is_trgo2_name(trig->name))
@ -169,10 +169,10 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,
0x2 << TIM_CR2_MMS_SHIFT);
/* Make sure that registers are updated */
regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
/* Enable controller */
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
mutex_unlock(&priv->lock);
return 0;
@ -189,19 +189,19 @@ static void stm32_timer_stop(struct stm32_timer_trigger *priv,
mutex_lock(&priv->lock);
/* Stop timer */
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
regmap_write(priv->regmap, TIM_PSC, 0);
regmap_write(priv->regmap, TIM_ARR, 0);
/* Force disable master mode */
if (stm32_timer_is_trgo2_name(trig->name))
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
else
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS);
/* Make sure that registers are updated */
regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
if (priv->enabled) {
priv->enabled = false;
@ -498,11 +498,9 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev,
priv->enabled = true;
clk_enable(priv->clk);
}
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
TIM_CR1_CEN);
regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
} else {
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
0);
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
if (priv->enabled) {
priv->enabled = false;
clk_disable(priv->clk);
@ -555,7 +553,7 @@ static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
{
struct stm32_timer_trigger *priv = iio_priv(indio_dev);
regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);
return 0;
}
@ -683,7 +681,7 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
return ret;
/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
regmap_write(priv->regmap, TIM_ARR, preset);
return len;
@ -757,9 +755,9 @@ static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
* Master mode selection 2 bits can only be written and read back when
* timer supports it.
*/
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
regmap_read(priv->regmap, TIM_CR2, &val);
regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
priv->has_trgo2 = !!val;
}
@ -820,7 +818,7 @@ static void stm32_timer_trigger_remove(struct platform_device *pdev)
/* Check if nobody else use the timer, then disable it */
regmap_read(priv->regmap, TIM_CCER, &val);
if (!(val & TIM_CCER_CCXE))
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
if (priv->enabled)
clk_disable(priv->clk);
@ -841,7 +839,7 @@ static int stm32_timer_trigger_suspend(struct device *dev)
regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
/* Disable the timer */
regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
clk_disable(priv->clk);
}