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ARM: realview/vexpress: consolidate SMP bringup code
Realview and Versatile Express share the same SMP bringup code, so consolidate the two implementations. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
cdab142a80
commit
0462b4477e
@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_REALVIEW_PB11MP) += realview_pb11mp.o
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obj-$(CONFIG_MACH_REALVIEW_PB1176) += realview_pb1176.o
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obj-$(CONFIG_MACH_REALVIEW_PBA8) += realview_pba8.o
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obj-$(CONFIG_MACH_REALVIEW_PBX) += realview_pbx.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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@ -1,40 +0,0 @@
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/*
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* linux/arch/arm/mach-realview/headsmp.S
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*
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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__INIT
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/*
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* Realview specific entry point for secondary CPUs. This provides
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* a "holding pen" into which all secondary cores are held until we're
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* ready for them to initialise.
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*/
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ENTRY(realview_secondary_startup)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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ldmia r4, {r5, r6}
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sub r4, r4, r5
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add r6, r6, r4
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pen: ldr r7, [r6]
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cmp r7, r0
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bne pen
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/*
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* we've been released from the holding pen: secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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.align
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1: .long .
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.long pen_release
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@ -10,44 +10,21 @@
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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#include <mach/board-eb.h>
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#include <mach/board-pb11mp.h>
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#include <mach/board-pbx.h>
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#include <asm/smp_scu.h>
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#include "core.h"
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extern void realview_secondary_startup(void);
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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extern void versatile_secondary_startup(void);
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static void __iomem *scu_base_addr(void)
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{
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@ -62,75 +39,6 @@ static void __iomem *scu_base_addr(void)
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return (void __iomem *)0;
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* The secondary processor is waiting to be released from
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* the holding pen - release it, then wait for it to flag
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* that it has been released by resetting pen_release.
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*
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* Note that "pen_release" is the hardware CPU ID, whereas
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* "cpu" is Linux's internal ID.
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*/
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write_pen_release(cpu);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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@ -174,6 +82,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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__raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
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__raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
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__io_address(REALVIEW_SYS_FLAGSSET));
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}
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@ -4,5 +4,5 @@
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obj-y := v2m.o
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obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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@ -10,13 +10,9 @@
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <asm/unified.h>
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@ -26,99 +22,13 @@
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#include "core.h"
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extern void vexpress_secondary_startup(void);
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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extern void versatile_secondary_startup(void);
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static void __iomem *scu_base_addr(void)
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{
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return MMIO_P2V(A9_MPCORE_SCU);
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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* CPUs in the holding pen until we're ready for them. However,
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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write_pen_release(cpu);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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@ -163,6 +73,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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* secondary CPU branches to this address.
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*/
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writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
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writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
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writel(BSYM(virt_to_phys(versatile_secondary_startup)),
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MMIO_P2V(V2M_SYS_FLAGSSET));
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}
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@ -4,4 +4,4 @@ obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
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obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
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obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
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obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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@ -1,5 +1,5 @@
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/*
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* linux/arch/arm/mach-vexpress/headsmp.S
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* linux/arch/arm/plat-versatile/headsmp.S
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*
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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@ -14,11 +14,11 @@
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__INIT
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/*
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* Versatile Express specific entry point for secondary CPUs. This
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* provides a "holding pen" into which all secondary cores are held
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* Realview/Versatile Express specific entry point for secondary CPUs.
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* This provides a "holding pen" into which all secondary cores are held
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* until we're ready for them to initialise.
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*/
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ENTRY(vexpress_secondary_startup)
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ENTRY(versatile_secondary_startup)
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #15
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adr r4, 1f
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104
arch/arm/plat-versatile/platsmp.c
Normal file
104
arch/arm/plat-versatile/platsmp.c
Normal file
@ -0,0 +1,104 @@
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/*
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* linux/arch/arm/plat-versatile/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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/*
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* control for which core is the next to come out of the secondary
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* boot "holding pen"
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*/
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volatile int __cpuinitdata pen_release = -1;
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/*
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* Write pen_release in a way that is guaranteed to be visible to all
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* observers, irrespective of whether they're taking part in coherency
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* or not. This is necessary for the hotplug code to work reliably.
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*/
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static void __cpuinit write_pen_release(int val)
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{
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pen_release = val;
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smp_wmb();
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__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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}
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static DEFINE_SPINLOCK(boot_lock);
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void __cpuinit platform_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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* CPUs in the holding pen until we're ready for them. However,
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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write_pen_release(cpu);
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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smp_cross_call(cpumask_of(cpu), 1);
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (pen_release == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return pen_release != -1 ? -ENOSYS : 0;
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}
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