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drm/msm: hdmi phy 8960 phy pll
On downstream kernel the clk driver directly bangs hdmi phy registers. For upstream kernel, we need to model this as a clock and register with the clock framework. Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark
parent
89301471e6
commit
034fbcc3d8
@ -15,13 +15,370 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "hdmi.h"
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struct hdmi_phy_8960 {
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struct hdmi_phy base;
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struct hdmi *hdmi;
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struct clk_hw pll_hw;
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struct clk *pll;
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unsigned long pixclk;
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};
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#define to_hdmi_phy_8960(x) container_of(x, struct hdmi_phy_8960, base)
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#define clk_to_phy(x) container_of(x, struct hdmi_phy_8960, pll_hw)
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/*
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* HDMI PLL:
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*
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* To get the parent clock setup properly, we need to plug in hdmi pll
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* configuration into common-clock-framework.
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*/
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struct pll_rate {
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unsigned long rate;
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struct {
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uint32_t val;
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uint32_t reg;
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} conf[32];
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};
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/* NOTE: keep sorted highest freq to lowest: */
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static const struct pll_rate freqtbl[] = {
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/* 1080p60/1080p50 case */
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{ 148500000, {
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{ 0x02, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
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{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
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{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
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{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
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{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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{ 0, 0 } }
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},
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{ 108000000, {
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{ 0x08, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x21, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x1c, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x49, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0, 0 } }
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},
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/* 720p60/720p50/1080i60/1080i50/1080p24/1080p30/1080p25 */
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{ 74250000, {
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x12, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x76, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0xe6, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0, 0 } }
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},
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{ 65000000, {
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{ 0x18, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xf9, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x8a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x0b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4b, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x09, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0, 0 } }
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},
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/* 480p60/480i60 */
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{ 27030000, {
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x38, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x20, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0xff, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4e, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0xd7, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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{ 0, 0 } }
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},
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/* 576p50/576i50 */
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{ 27000000, {
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{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
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{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x7b, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x01, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
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{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
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{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
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{ 0x2a, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x03, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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{ 0, 0 } }
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},
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/* 640x480p60 */
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{ 25200000, {
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{ 0x32, REG_HDMI_8960_PHY_PLL_REFCLK_CFG },
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{ 0x02, REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG },
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{ 0x01, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 },
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{ 0x2c, REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG },
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{ 0x06, REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG },
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{ 0x0a, REG_HDMI_8960_PHY_PLL_PWRDN_B },
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{ 0x77, REG_HDMI_8960_PHY_PLL_SDM_CFG0 },
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{ 0x4c, REG_HDMI_8960_PHY_PLL_SDM_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG2 },
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{ 0xc0, REG_HDMI_8960_PHY_PLL_SDM_CFG3 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SDM_CFG4 },
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{ 0x9a, REG_HDMI_8960_PHY_PLL_SSC_CFG0 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG1 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_SSC_CFG2 },
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{ 0x20, REG_HDMI_8960_PHY_PLL_SSC_CFG3 },
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{ 0x10, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 },
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{ 0x1a, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 },
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{ 0x0d, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 },
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{ 0xf4, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 },
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{ 0x02, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 },
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{ 0x3b, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 },
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{ 0x86, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 },
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{ 0x33, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 },
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{ 0x00, REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 },
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{ 0, 0 } }
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},
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};
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static int hdmi_pll_enable(struct clk_hw *hw)
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{
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struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
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struct hdmi *hdmi = phy_8960->hdmi;
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int timeout_count, pll_lock_retry = 10;
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unsigned int val;
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DBG("");
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/* Assert PLL S/W reset */
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0, 0x10);
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1, 0x1a);
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/* Wait for a short time before de-asserting
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* to allow the hardware to complete its job.
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* This much of delay should be fine for hardware
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* to assert and de-assert.
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*/
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udelay(10);
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/* De-assert PLL S/W reset */
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
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val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
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val |= HDMI_8960_PHY_REG12_SW_RESET;
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/* Assert PHY S/W reset */
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hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
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val &= ~HDMI_8960_PHY_REG12_SW_RESET;
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/* Wait for a short time before de-asserting
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to allow the hardware to complete its job.
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This much of delay should be fine for hardware
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to assert and de-assert. */
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udelay(10);
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/* De-assert PHY S/W reset */
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hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
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hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x3f);
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val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
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val |= HDMI_8960_PHY_REG12_PWRDN_B;
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hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
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/* Wait 10 us for enabling global power for PHY */
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mb();
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udelay(10);
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val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B);
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val |= HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B;
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val &= ~HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL;
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
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hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x80);
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timeout_count = 1000;
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while (--pll_lock_retry > 0) {
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/* are we there yet? */
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val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_STATUS0);
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if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK)
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break;
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udelay(1);
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if (--timeout_count > 0)
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continue;
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/*
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* PLL has still not locked.
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* Do a software reset and try again
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* Assert PLL S/W reset first
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*/
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x8d);
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udelay(10);
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2, 0x0d);
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/*
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* Wait for a short duration for the PLL calibration
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* before checking if the PLL gets locked
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*/
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udelay(350);
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timeout_count = 1000;
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}
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return 0;
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}
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static void hdmi_pll_disable(struct clk_hw *hw)
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{
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struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
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struct hdmi *hdmi = phy_8960->hdmi;
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unsigned int val;
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DBG("");
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val = hdmi_read(hdmi, REG_HDMI_8960_PHY_REG12);
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val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
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hdmi_write(hdmi, REG_HDMI_8960_PHY_REG12, val);
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val = hdmi_read(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B);
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val |= HDMI_8960_PHY_REG12_SW_RESET;
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val &= ~HDMI_8960_PHY_REG12_PWRDN_B;
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hdmi_write(hdmi, REG_HDMI_8960_PHY_PLL_PWRDN_B, val);
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/* Make sure HDMI PHY/PLL are powered down */
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mb();
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}
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static const struct pll_rate *find_rate(unsigned long rate)
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{
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int i;
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for (i = 1; i < ARRAY_SIZE(freqtbl); i++)
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if (rate > freqtbl[i].rate)
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return &freqtbl[i-1];
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return &freqtbl[i-1];
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}
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static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
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return phy_8960->pixclk;
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}
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static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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const struct pll_rate *pll_rate = find_rate(rate);
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return pll_rate->rate;
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}
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static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct hdmi_phy_8960 *phy_8960 = clk_to_phy(hw);
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struct hdmi *hdmi = phy_8960->hdmi;
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const struct pll_rate *pll_rate = find_rate(rate);
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int i;
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DBG("rate=%lu", rate);
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for (i = 0; pll_rate->conf[i].reg; i++)
|
||||
hdmi_write(hdmi, pll_rate->conf[i].reg, pll_rate->conf[i].val);
|
||||
|
||||
phy_8960->pixclk = rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static const struct clk_ops hdmi_pll_ops = {
|
||||
.enable = hdmi_pll_enable,
|
||||
.disable = hdmi_pll_disable,
|
||||
.recalc_rate = hdmi_pll_recalc_rate,
|
||||
.round_rate = hdmi_pll_round_rate,
|
||||
.set_rate = hdmi_pll_set_rate,
|
||||
};
|
||||
|
||||
static const char *hdmi_pll_parents[] = {
|
||||
"pxo",
|
||||
};
|
||||
|
||||
static struct clk_init_data pll_init = {
|
||||
.name = "hdmi_pll",
|
||||
.ops = &hdmi_pll_ops,
|
||||
.parent_names = hdmi_pll_parents,
|
||||
.num_parents = ARRAY_SIZE(hdmi_pll_parents),
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* HDMI Phy:
|
||||
*/
|
||||
|
||||
static void hdmi_phy_8960_destroy(struct hdmi_phy *phy)
|
||||
{
|
||||
@ -86,6 +443,9 @@ static void hdmi_phy_8960_powerup(struct hdmi_phy *phy,
|
||||
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
|
||||
struct hdmi *hdmi = phy_8960->hdmi;
|
||||
|
||||
DBG("pixclock: %lu", pixclock);
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x00);
|
||||
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG0, 0x1b);
|
||||
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG1, 0xf2);
|
||||
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG4, 0x00);
|
||||
@ -104,6 +464,8 @@ static void hdmi_phy_8960_powerdown(struct hdmi_phy *phy)
|
||||
struct hdmi_phy_8960 *phy_8960 = to_hdmi_phy_8960(phy);
|
||||
struct hdmi *hdmi = phy_8960->hdmi;
|
||||
|
||||
DBG("");
|
||||
|
||||
hdmi_write(hdmi, REG_HDMI_8960_PHY_REG2, 0x7f);
|
||||
}
|
||||
|
||||
@ -118,7 +480,12 @@ struct hdmi_phy *hdmi_phy_8960_init(struct hdmi *hdmi)
|
||||
{
|
||||
struct hdmi_phy_8960 *phy_8960;
|
||||
struct hdmi_phy *phy = NULL;
|
||||
int ret;
|
||||
int ret, i;
|
||||
|
||||
/* sanity check: */
|
||||
for (i = 0; i < (ARRAY_SIZE(freqtbl) - 1); i++)
|
||||
if (WARN_ON(freqtbl[i].rate < freqtbl[i+1].rate))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
phy_8960 = kzalloc(sizeof(*phy_8960), GFP_KERNEL);
|
||||
if (!phy_8960) {
|
||||
@ -132,6 +499,14 @@ struct hdmi_phy *hdmi_phy_8960_init(struct hdmi *hdmi)
|
||||
|
||||
phy_8960->hdmi = hdmi;
|
||||
|
||||
phy_8960->pll_hw.init = &pll_init;
|
||||
phy_8960->pll = devm_clk_register(hdmi->dev->dev, &phy_8960->pll_hw);
|
||||
if (IS_ERR(phy_8960->pll)) {
|
||||
ret = PTR_ERR(phy_8960->pll);
|
||||
phy_8960->pll = NULL;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return phy;
|
||||
|
||||
fail:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user