mirror of
https://github.com/torvalds/linux.git
synced 2024-11-20 02:51:44 +00:00
dt-bindings: display: dw-hdmi: Clean up DT bindings documentation
Make it clear that the core bridge/dw_hdmi.txt document isn't a device tree binding by itself but is meant to be referenced by platform device tree bindings, and update the Rockchip and Freescale DWC HDMI TX bindings to reference it. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-21-laurent.pinchart+renesas@ideasonboard.com
This commit is contained in:
Laurent Pinchart
Archit Taneja
parent
2668db3788
commit
01f8c951c2
@ -1,52 +1,33 @@
|
||||
DesignWare HDMI bridge bindings
|
||||
Synopsys DesignWare HDMI TX Encoder
|
||||
===================================
|
||||
|
||||
Required properties:
|
||||
- compatible: platform specific such as:
|
||||
* "snps,dw-hdmi-tx"
|
||||
* "fsl,imx6q-hdmi"
|
||||
* "fsl,imx6dl-hdmi"
|
||||
* "rockchip,rk3288-dw-hdmi"
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- interrupts: The HDMI interrupt number
|
||||
- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
|
||||
as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
|
||||
the clocks are soc specific, the clock-names should be "iahb", "isfr"
|
||||
-port@[X]: SoC specific port nodes with endpoint definitions as defined
|
||||
in Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||
please refer to the SoC specific binding document:
|
||||
* Documentation/devicetree/bindings/display/imx/hdmi.txt
|
||||
* Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
|
||||
This document defines device tree properties for the Synopsys DesignWare HDMI
|
||||
TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
|
||||
specification by itself but is meant to be referenced by platform-specific
|
||||
device tree bindings.
|
||||
|
||||
Optional properties
|
||||
- reg-io-width: the width of the reg:1,4, default set to 1 if not present
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
|
||||
if the property is omitted, a functionally reduced I2C bus
|
||||
controller on DW HDMI is probed
|
||||
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
|
||||
When referenced from platform device tree bindings the properties defined in
|
||||
this document are defined as follows. The platform device tree bindings are
|
||||
responsible for defining whether each property is required or optional.
|
||||
|
||||
Example:
|
||||
hdmi: hdmi@0120000 {
|
||||
compatible = "fsl,imx6q-hdmi";
|
||||
reg = <0x00120000 0x9000>;
|
||||
interrupts = <0 115 0x04>;
|
||||
gpr = <&gpr>;
|
||||
clocks = <&clks 123>, <&clks 124>;
|
||||
clock-names = "iahb", "isfr";
|
||||
ddc-i2c-bus = <&i2c2>;
|
||||
- reg: Memory mapped base address and length of the DWC HDMI TX registers.
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
- reg-io-width: Width of the registers specified by the reg property. The
|
||||
value is expressed in bytes and must be equal to 1 or 4 if specified. The
|
||||
register width defaults to 1 if the property is not present.
|
||||
|
||||
hdmi_mux_0: endpoint {
|
||||
remote-endpoint = <&ipu1_di0_hdmi>;
|
||||
};
|
||||
};
|
||||
- interrupts: Reference to the DWC HDMI TX interrupt.
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
- clocks: References to all the clocks specified in the clock-names property
|
||||
as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
|
||||
|
||||
hdmi_mux_1: endpoint {
|
||||
remote-endpoint = <&ipu1_di1_hdmi>;
|
||||
};
|
||||
};
|
||||
};
|
||||
- clock-names: The DWC HDMI TX uses the following clocks.
|
||||
|
||||
- "iahb" is the bus clock for either AHB and APB (mandatory).
|
||||
- "isfr" is the internal register configuration clock (mandatory).
|
||||
- "cec" is the HDMI CEC controller main clock (optional).
|
||||
|
||||
- ports: The connectivity of the DWC HDMI TX with the rest of the system is
|
||||
expressed in using ports as specified in the device graph bindings defined
|
||||
in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
|
||||
is platform-specific.
|
||||
|
||||
@ -1,29 +1,36 @@
|
||||
Device-Tree bindings for HDMI Transmitter
|
||||
Freescale i.MX6 DWC HDMI TX Encoder
|
||||
===================================
|
||||
|
||||
HDMI Transmitter
|
||||
================
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with accompanying PHY IP.
|
||||
|
||||
Required properties:
|
||||
- #address-cells : should be <1>
|
||||
- #size-cells : should be <0>
|
||||
- compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
||||
- gpr : should be <&gpr>.
|
||||
The phandle points to the iomuxc-gpr region containing the HDMI
|
||||
multiplexer control register.
|
||||
- clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
|
||||
in Documentation/devicetree/bindings/clock/clock-bindings.txt and
|
||||
Documentation/devicetree/bindings/clock/imx6q-clock.txt.
|
||||
- port@[0-4]: Up to four port nodes with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt,
|
||||
corresponding to the four inputs to the HDMI multiplexer.
|
||||
|
||||
Optional properties:
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
|
||||
- reg: See dw_hdmi.txt.
|
||||
- interrupts: HDMI interrupt number
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
|
||||
numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.
|
||||
Each port shall have a single endpoint.
|
||||
- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI
|
||||
multiplexer control register.
|
||||
|
||||
example:
|
||||
Optional properties
|
||||
|
||||
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||
connected to a system I2C master this property contains a phandle to that
|
||||
I2C master controller.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
gpr: iomuxc-gpr@020e0000 {
|
||||
/* ... */
|
||||
|
||||
@ -1,24 +1,39 @@
|
||||
Rockchip specific extensions to the Synopsys Designware HDMI
|
||||
================================
|
||||
Rockchip DWC HDMI TX Encoder
|
||||
============================
|
||||
|
||||
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
|
||||
with a companion PHY IP.
|
||||
|
||||
These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
||||
Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
|
||||
following device-specific properties.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: "rockchip,rk3288-dw-hdmi";
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
- clocks: phandle to hdmi iahb and isfr clocks.
|
||||
- clock-names: should be "iahb" "isfr"
|
||||
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
|
||||
|
||||
- compatible: Shall contain "rockchip,rk3288-dw-hdmi".
|
||||
- reg: See dw_hdmi.txt.
|
||||
- reg-io-width: See dw_hdmi.txt. Shall be 4.
|
||||
- interrupts: HDMI interrupt number
|
||||
- ports: contain a port node with endpoint definitions as defined in
|
||||
Documentation/devicetree/bindings/media/video-interfaces.txt. For
|
||||
vopb,set the reg = <0> and set the reg = <1> for vopl.
|
||||
- reg-io-width: the width of the reg:1,4, the value should be 4 on
|
||||
rk3288 platform
|
||||
- clocks: See dw_hdmi.txt.
|
||||
- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
|
||||
- ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
|
||||
corresponding to the video input of the controller. The port shall have two
|
||||
endpoints, numbered 0 and 1, connected respectively to the vopb and vopl.
|
||||
- rockchip,grf: Shall reference the GRF to mux vopl/vopb.
|
||||
|
||||
Optional properties
|
||||
- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
|
||||
- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
|
||||
|
||||
- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
|
||||
or the functionally-reduced I2C master contained in the DWC HDMI. When
|
||||
connected to a system I2C master this property contains a phandle to that
|
||||
I2C master controller.
|
||||
- clock-names: See dw_hdmi.txt. The "cec" clock is optional.
|
||||
- clock-names: May contain "cec" as defined in dw_hdmi.txt.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
hdmi: hdmi@ff980000 {
|
||||
compatible = "rockchip,rk3288-dw-hdmi";
|
||||
reg = <0xff980000 0x20000>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user