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riscv: add alignment for text, rodata and data sections

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The kernel mapping will tried to optimize its mapping by using bigger
size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in
rv32. To ensure that the start address of these sections could fit the
mapping entry size, make them align to the biggest alignment.

Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc.,
are invisible in linker script.

This patch is prepared for STRICT_KERNEL_RWX support.

Signed-off-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Zong Li 2020-03-10 00:55:40 +08:00 committed by Palmer Dabbelt
parent bd3d914d16
commit 00cb41d5ad
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GPG Key ID: 2E1319F35FBB1889
2 changed files with 17 additions and 1 deletions
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13
arch/riscv/include/asm/set_memory.h
View File

@ -6,6 +6,7 @@
#ifndef _ASM_RISCV_SET_MEMORY_H #ifndef _ASM_RISCV_SET_MEMORY_H
#define _ASM_RISCV_SET_MEMORY_H #define _ASM_RISCV_SET_MEMORY_H
#ifndef __ASSEMBLY__
/* /*
* Functions to change memory attributes. * Functions to change memory attributes.
*/ */
@ -24,4 +25,16 @@ static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
int set_direct_map_invalid_noflush(struct page *page); int set_direct_map_invalid_noflush(struct page *page);
int set_direct_map_default_noflush(struct page *page); int set_direct_map_default_noflush(struct page *page);
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
#ifdef CONFIG_64BIT
#define SECTION_ALIGN (1 << 21)
#else
#define SECTION_ALIGN (1 << 22)
#endif
#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
#define SECTION_ALIGN L1_CACHE_BYTES
#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
#endif /* _ASM_RISCV_SET_MEMORY_H */ #endif /* _ASM_RISCV_SET_MEMORY_H */

5
arch/riscv/kernel/vmlinux.lds.S
View File

@ -9,6 +9,7 @@
#include <asm/page.h> #include <asm/page.h>
#include <asm/cache.h> #include <asm/cache.h>
#include <asm/thread_info.h> #include <asm/thread_info.h>
#include <asm/set_memory.h>
OUTPUT_ARCH(riscv) OUTPUT_ARCH(riscv)
ENTRY(_start) ENTRY(_start)
@ -36,6 +37,7 @@ SECTIONS
PERCPU_SECTION(L1_CACHE_BYTES) PERCPU_SECTION(L1_CACHE_BYTES)
__init_end = .; __init_end = .;
. = ALIGN(SECTION_ALIGN);
.text : { .text : {
_text = .; _text = .;
_stext = .; _stext = .;
@ -53,13 +55,14 @@ SECTIONS
/* Start of data section */ /* Start of data section */
_sdata = .; _sdata = .;
RO_DATA(L1_CACHE_BYTES) RO_DATA(SECTION_ALIGN)
.srodata : { .srodata : {
*(.srodata*) *(.srodata*)
} }
EXCEPTION_TABLE(0x10) EXCEPTION_TABLE(0x10)
. = ALIGN(SECTION_ALIGN);
_data = .; _data = .;
RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)