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riscv: add alignment for text, rodata and data sections
The kernel mapping will tried to optimize its mapping by using bigger size. In rv64, it tries to use PMD_SIZE, and tryies to use PGDIR_SIZE in rv32. To ensure that the start address of these sections could fit the mapping entry size, make them align to the biggest alignment. Define a macro SECTION_ALIGN because the HPAGE_SIZE or PMD_SIZE, etc., are invisible in linker script. This patch is prepared for STRICT_KERNEL_RWX support. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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@ -6,6 +6,7 @@
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#ifndef _ASM_RISCV_SET_MEMORY_H
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#define _ASM_RISCV_SET_MEMORY_H
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#ifndef __ASSEMBLY__
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/*
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* Functions to change memory attributes.
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*/
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@ -24,4 +25,16 @@ static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
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int set_direct_map_invalid_noflush(struct page *page);
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int set_direct_map_default_noflush(struct page *page);
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_ARCH_HAS_STRICT_KERNEL_RWX
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#ifdef CONFIG_64BIT
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#define SECTION_ALIGN (1 << 21)
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#else
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#define SECTION_ALIGN (1 << 22)
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#endif
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#else /* !CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
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#define SECTION_ALIGN L1_CACHE_BYTES
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#endif /* CONFIG_ARCH_HAS_STRICT_KERNEL_RWX */
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#endif /* _ASM_RISCV_SET_MEMORY_H */
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@ -9,6 +9,7 @@
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/set_memory.h>
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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@ -36,6 +37,7 @@ SECTIONS
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PERCPU_SECTION(L1_CACHE_BYTES)
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__init_end = .;
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. = ALIGN(SECTION_ALIGN);
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.text : {
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_text = .;
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_stext = .;
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@ -53,13 +55,14 @@ SECTIONS
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/* Start of data section */
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_sdata = .;
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RO_DATA(L1_CACHE_BYTES)
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RO_DATA(SECTION_ALIGN)
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.srodata : {
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*(.srodata*)
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}
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EXCEPTION_TABLE(0x10)
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. = ALIGN(SECTION_ALIGN);
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_data = .;
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RW_DATA(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
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