2018-04-17 03:43:36 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Lattice MachXO2 Slave SPI Driver
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*
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* Manage Lattice FPGA firmware that is loaded over SPI using
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* the slave serial configuration interface.
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*
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* Copyright (C) 2018 Paolo Pisati <p.pisati@gmail.com>
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*/
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#include <linux/delay.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/gpio/consumer.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/spi/spi.h>
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/* MachXO2 Programming Guide - sysCONFIG Programming Commands */
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#define IDCODE_PUB {0xe0, 0x00, 0x00, 0x00}
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#define ISC_ENABLE {0xc6, 0x08, 0x00, 0x00}
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#define ISC_ERASE {0x0e, 0x04, 0x00, 0x00}
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#define ISC_PROGRAMDONE {0x5e, 0x00, 0x00, 0x00}
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#define LSC_INITADDRESS {0x46, 0x00, 0x00, 0x00}
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#define LSC_PROGINCRNV {0x70, 0x00, 0x00, 0x01}
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#define LSC_READ_STATUS {0x3c, 0x00, 0x00, 0x00}
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#define LSC_REFRESH {0x79, 0x00, 0x00, 0x00}
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/*
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* Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
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* Sheet' sysCONFIG Port Timing Specifications (3-36)
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*/
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#define MACHXO2_MAX_SPEED 66000000
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#define MACHXO2_LOW_DELAY_USEC 5
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#define MACHXO2_HIGH_DELAY_USEC 200
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#define MACHXO2_REFRESH_USEC 4800
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#define MACHXO2_MAX_BUSY_LOOP 128
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#define MACHXO2_MAX_REFRESH_LOOP 16
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#define MACHXO2_PAGE_SIZE 16
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#define MACHXO2_BUF_SIZE (MACHXO2_PAGE_SIZE + 4)
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/* Status register bits, errors and error mask */
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#define BUSY 12
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#define DONE 8
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#define DVER 27
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#define ENAB 9
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#define ERRBITS 23
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#define ERRMASK 7
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#define FAIL 13
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#define ENOERR 0 /* no error */
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#define EID 1
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#define ECMD 2
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#define ECRC 3
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#define EPREAM 4 /* preamble error */
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#define EABRT 5 /* abort error */
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#define EOVERFL 6 /* overflow error */
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#define ESDMEOF 7 /* SDM EOF */
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static inline u8 get_err(unsigned long *status)
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{
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return (*status >> ERRBITS) & ERRMASK;
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}
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static int get_status(struct spi_device *spi, unsigned long *status)
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{
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struct spi_message msg;
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struct spi_transfer rx, tx;
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static const u8 cmd[] = LSC_READ_STATUS;
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int ret;
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memset(&rx, 0, sizeof(rx));
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memset(&tx, 0, sizeof(tx));
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tx.tx_buf = cmd;
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tx.len = sizeof(cmd);
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rx.rx_buf = status;
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rx.len = 4;
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spi_message_init(&msg);
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spi_message_add_tail(&tx, &msg);
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spi_message_add_tail(&rx, &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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return ret;
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*status = be32_to_cpu(*status);
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return 0;
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}
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#ifdef DEBUG
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static const char *get_err_string(u8 err)
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{
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switch (err) {
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case ENOERR: return "No Error";
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case EID: return "ID ERR";
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case ECMD: return "CMD ERR";
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case ECRC: return "CRC ERR";
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case EPREAM: return "Preamble ERR";
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case EABRT: return "Abort ERR";
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case EOVERFL: return "Overflow ERR";
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case ESDMEOF: return "SDM EOF";
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}
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return "Default switch case";
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}
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#endif
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static void dump_status_reg(unsigned long *status)
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{
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#ifdef DEBUG
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pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
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*status, test_bit(DONE, status), test_bit(ENAB, status),
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test_bit(BUSY, status), test_bit(FAIL, status),
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test_bit(DVER, status), get_err_string(get_err(status)));
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#endif
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}
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static int wait_until_not_busy(struct spi_device *spi)
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{
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unsigned long status;
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int ret, loop = 0;
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do {
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ret = get_status(spi, &status);
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if (ret)
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return ret;
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if (++loop >= MACHXO2_MAX_BUSY_LOOP)
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return -EBUSY;
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} while (test_bit(BUSY, &status));
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return 0;
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}
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static int machxo2_cleanup(struct fpga_manager *mgr)
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{
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struct spi_device *spi = mgr->priv;
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struct spi_message msg;
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struct spi_transfer tx[2];
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static const u8 erase[] = ISC_ERASE;
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static const u8 refresh[] = LSC_REFRESH;
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int ret;
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memset(tx, 0, sizeof(tx));
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spi_message_init(&msg);
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tx[0].tx_buf = &erase;
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tx[0].len = sizeof(erase);
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spi_message_add_tail(&tx[0], &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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goto fail;
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ret = wait_until_not_busy(spi);
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if (ret)
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goto fail;
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spi_message_init(&msg);
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tx[1].tx_buf = &refresh;
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tx[1].len = sizeof(refresh);
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2020-02-27 14:24:14 +00:00
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tx[1].delay.value = MACHXO2_REFRESH_USEC;
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tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
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2018-04-17 03:43:36 +00:00
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spi_message_add_tail(&tx[1], &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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goto fail;
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return 0;
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fail:
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dev_err(&mgr->dev, "Cleanup failed\n");
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return ret;
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}
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static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
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{
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struct spi_device *spi = mgr->priv;
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unsigned long status;
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get_status(spi, &status);
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if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
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get_err(&status) == ENOERR)
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return FPGA_MGR_STATE_OPERATING;
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return FPGA_MGR_STATE_UNKNOWN;
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}
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static int machxo2_write_init(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct spi_device *spi = mgr->priv;
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struct spi_message msg;
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struct spi_transfer tx[3];
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static const u8 enable[] = ISC_ENABLE;
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static const u8 erase[] = ISC_ERASE;
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static const u8 initaddr[] = LSC_INITADDRESS;
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unsigned long status;
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int ret;
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if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
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dev_err(&mgr->dev,
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"Partial reconfiguration is not supported\n");
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return -ENOTSUPP;
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}
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get_status(spi, &status);
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dump_status_reg(&status);
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memset(tx, 0, sizeof(tx));
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spi_message_init(&msg);
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tx[0].tx_buf = &enable;
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tx[0].len = sizeof(enable);
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2020-02-27 14:24:14 +00:00
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tx[0].delay.value = MACHXO2_LOW_DELAY_USEC;
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tx[0].delay.unit = SPI_DELAY_UNIT_USECS;
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2018-04-17 03:43:36 +00:00
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spi_message_add_tail(&tx[0], &msg);
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tx[1].tx_buf = &erase;
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tx[1].len = sizeof(erase);
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spi_message_add_tail(&tx[1], &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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goto fail;
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ret = wait_until_not_busy(spi);
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if (ret)
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goto fail;
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get_status(spi, &status);
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2021-08-10 16:40:36 +00:00
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if (test_bit(FAIL, &status)) {
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ret = -EINVAL;
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2018-04-17 03:43:36 +00:00
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goto fail;
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2021-08-10 16:40:36 +00:00
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}
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2018-04-17 03:43:36 +00:00
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dump_status_reg(&status);
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spi_message_init(&msg);
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tx[2].tx_buf = &initaddr;
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tx[2].len = sizeof(initaddr);
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spi_message_add_tail(&tx[2], &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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goto fail;
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get_status(spi, &status);
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dump_status_reg(&status);
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return 0;
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fail:
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dev_err(&mgr->dev, "Error during FPGA init.\n");
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return ret;
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}
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static int machxo2_write(struct fpga_manager *mgr, const char *buf,
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size_t count)
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{
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struct spi_device *spi = mgr->priv;
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struct spi_message msg;
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struct spi_transfer tx;
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static const u8 progincr[] = LSC_PROGINCRNV;
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u8 payload[MACHXO2_BUF_SIZE];
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unsigned long status;
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int i, ret;
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if (count % MACHXO2_PAGE_SIZE != 0) {
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dev_err(&mgr->dev, "Malformed payload.\n");
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return -EINVAL;
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}
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get_status(spi, &status);
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dump_status_reg(&status);
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memcpy(payload, &progincr, sizeof(progincr));
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for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
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memcpy(&payload[sizeof(progincr)], &buf[i], MACHXO2_PAGE_SIZE);
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memset(&tx, 0, sizeof(tx));
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spi_message_init(&msg);
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tx.tx_buf = payload;
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tx.len = MACHXO2_BUF_SIZE;
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2020-02-27 14:24:14 +00:00
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tx.delay.value = MACHXO2_HIGH_DELAY_USEC;
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tx.delay.unit = SPI_DELAY_UNIT_USECS;
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2018-04-17 03:43:36 +00:00
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spi_message_add_tail(&tx, &msg);
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ret = spi_sync(spi, &msg);
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if (ret) {
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dev_err(&mgr->dev, "Error loading the bitstream.\n");
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return ret;
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}
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}
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get_status(spi, &status);
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dump_status_reg(&status);
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return 0;
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}
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static int machxo2_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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struct spi_device *spi = mgr->priv;
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struct spi_message msg;
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struct spi_transfer tx[2];
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static const u8 progdone[] = ISC_PROGRAMDONE;
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static const u8 refresh[] = LSC_REFRESH;
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unsigned long status;
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int ret, refreshloop = 0;
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memset(tx, 0, sizeof(tx));
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spi_message_init(&msg);
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tx[0].tx_buf = &progdone;
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tx[0].len = sizeof(progdone);
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spi_message_add_tail(&tx[0], &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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goto fail;
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ret = wait_until_not_busy(spi);
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if (ret)
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goto fail;
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get_status(spi, &status);
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dump_status_reg(&status);
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if (!test_bit(DONE, &status)) {
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machxo2_cleanup(mgr);
|
2021-08-10 16:40:36 +00:00
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ret = -EINVAL;
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2018-04-17 03:43:36 +00:00
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goto fail;
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}
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do {
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spi_message_init(&msg);
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tx[1].tx_buf = &refresh;
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tx[1].len = sizeof(refresh);
|
2020-02-27 14:24:14 +00:00
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tx[1].delay.value = MACHXO2_REFRESH_USEC;
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tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
|
2018-04-17 03:43:36 +00:00
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spi_message_add_tail(&tx[1], &msg);
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ret = spi_sync(spi, &msg);
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if (ret)
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goto fail;
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/* check refresh status */
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get_status(spi, &status);
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dump_status_reg(&status);
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if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
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get_err(&status) == ENOERR)
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break;
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if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
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machxo2_cleanup(mgr);
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2021-08-13 06:40:42 +00:00
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ret = -EINVAL;
|
2018-04-17 03:43:36 +00:00
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goto fail;
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}
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} while (1);
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get_status(spi, &status);
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dump_status_reg(&status);
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return 0;
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fail:
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dev_err(&mgr->dev, "Refresh failed.\n");
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return ret;
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}
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static const struct fpga_manager_ops machxo2_ops = {
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.state = machxo2_spi_state,
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.write_init = machxo2_write_init,
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.write = machxo2_write,
|
|
|
|
.write_complete = machxo2_write_complete,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int machxo2_spi_probe(struct spi_device *spi)
|
|
|
|
{
|
|
|
|
struct device *dev = &spi->dev;
|
2018-05-16 23:49:55 +00:00
|
|
|
struct fpga_manager *mgr;
|
2018-04-17 03:43:36 +00:00
|
|
|
|
|
|
|
if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
|
|
|
|
dev_err(dev, "Speed is too high\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-11-19 01:55:51 +00:00
|
|
|
mgr = devm_fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
|
|
|
|
&machxo2_ops, spi);
|
|
|
|
return PTR_ERR_OR_ZERO(mgr);
|
2018-04-17 03:43:36 +00:00
|
|
|
}
|
|
|
|
|
2021-06-18 22:46:18 +00:00
|
|
|
#ifdef CONFIG_OF
|
2018-04-17 03:43:36 +00:00
|
|
|
static const struct of_device_id of_match[] = {
|
|
|
|
{ .compatible = "lattice,machxo2-slave-spi", },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, of_match);
|
2021-06-18 22:46:18 +00:00
|
|
|
#endif
|
2018-04-17 03:43:36 +00:00
|
|
|
|
|
|
|
static const struct spi_device_id lattice_ids[] = {
|
|
|
|
{ "machxo2-slave-spi", 0 },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(spi, lattice_ids);
|
|
|
|
|
|
|
|
static struct spi_driver machxo2_spi_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "machxo2-slave-spi",
|
|
|
|
.of_match_table = of_match_ptr(of_match),
|
|
|
|
},
|
|
|
|
.probe = machxo2_spi_probe,
|
|
|
|
.id_table = lattice_ids,
|
|
|
|
};
|
|
|
|
|
|
|
|
module_spi_driver(machxo2_spi_driver)
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>");
|
|
|
|
MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
|
|
|
|
MODULE_LICENSE("GPL v2");
|