License cleanup: add SPDX GPL-2.0 license identifier to files with no license
Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.
By default all files without license information are under the default
license of the kernel, which is GPL version 2.
Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.
This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.
How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,
Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.
The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.
The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.
Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if <5
lines).
All documentation files were explicitly excluded.
The following heuristics were used to determine which SPDX license
identifiers to apply.
- when both scanners couldn't find any license traces, file was
considered to have no license information in it, and the top level
COPYING file license applied.
For non */uapi/* files that summary was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 11139
and resulted in the first patch in this series.
If that file was a */uapi/* path one, it was "GPL-2.0 WITH
Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was:
SPDX license identifier # files
---------------------------------------------------|-------
GPL-2.0 WITH Linux-syscall-note 930
and resulted in the second patch in this series.
- if a file had some form of licensing information in it, and was one
of the */uapi/* ones, it was denoted with the Linux-syscall-note if
any GPL family license was found in the file or had no licensing in
it (per prior point). Results summary:
SPDX license identifier # files
---------------------------------------------------|------
GPL-2.0 WITH Linux-syscall-note 270
GPL-2.0+ WITH Linux-syscall-note 169
((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21
((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17
LGPL-2.1+ WITH Linux-syscall-note 15
GPL-1.0+ WITH Linux-syscall-note 14
((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5
LGPL-2.0+ WITH Linux-syscall-note 4
LGPL-2.1 WITH Linux-syscall-note 3
((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3
((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1
and that resulted in the third patch in this series.
- when the two scanners agreed on the detected license(s), that became
the concluded license(s).
- when there was disagreement between the two scanners (one detected a
license but the other didn't, or they both detected different
licenses) a manual inspection of the file occurred.
- In most cases a manual inspection of the information in the file
resulted in a clear resolution of the license that should apply (and
which scanner probably needed to revisit its heuristics).
- When it was not immediately clear, the license identifier was
confirmed with lawyers working with the Linux Foundation.
- If there was any question as to the appropriate license identifier,
the file was flagged for further research and to be revisited later
in time.
In total, over 70 hours of logged manual review was done on the
spreadsheet to determine the SPDX license identifiers to apply to the
source files by Kate, Philippe, Thomas and, in some cases, confirmation
by lawyers working with the Linux Foundation.
Kate also obtained a third independent scan of the 4.13 code base from
FOSSology, and compared selected files where the other two scanners
disagreed against that SPDX file, to see if there was new insights. The
Windriver scanner is based on an older version of FOSSology in part, so
they are related.
Thomas did random spot checks in about 500 files from the spreadsheets
for the uapi headers and agreed with SPDX license identifier in the
files he inspected. For the non-uapi files Thomas did random spot checks
in about 15000 files.
In initial set of patches against 4.14-rc6, 3 files were found to have
copy/paste license identifier errors, and have been fixed to reflect the
correct identifier.
Additionally Philippe spent 10 hours this week doing a detailed manual
inspection and review of the 12,461 patched files from the initial patch
version early this week with:
- a full scancode scan run, collecting the matched texts, detected
license ids and scores
- reviewing anything where there was a license detected (about 500+
files) to ensure that the applied SPDX license was correct
- reviewing anything where there was no detection but the patch license
was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied
SPDX license was correct
This produced a worksheet with 20 files needing minor correction. This
worksheet was then exported into 3 different .csv files for the
different types of files to be modified.
These .csv files were then reviewed by Greg. Thomas wrote a script to
parse the csv files and add the proper SPDX tag to the file, in the
format that the file expected. This script was further refined by Greg
based on the output to detect more types of files automatically and to
distinguish between header and source .c files (which need different
comment types.) Finally Greg ran the script using the .csv files to
generate the patches.
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-11-01 14:07:57 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
2021-11-15 18:19:13 +00:00
|
|
|
#ifndef __SPI_DW_H__
|
|
|
|
|
#define __SPI_DW_H__
|
2010-12-24 05:59:11 +00:00
|
|
|
|
2020-09-20 11:28:53 +00:00
|
|
|
#include <linux/bits.h>
|
2020-05-29 13:11:52 +00:00
|
|
|
#include <linux/completion.h>
|
2020-05-29 13:12:04 +00:00
|
|
|
#include <linux/debugfs.h>
|
2020-05-06 15:30:21 +00:00
|
|
|
#include <linux/irqreturn.h>
|
2009-12-14 22:20:22 +00:00
|
|
|
#include <linux/io.h>
|
2011-03-18 09:41:17 +00:00
|
|
|
#include <linux/scatterlist.h>
|
2020-10-07 23:55:06 +00:00
|
|
|
#include <linux/spi/spi-mem.h>
|
spi: dw: Add support for 32-bits max xfer size
The Synopsis DesignWare DW_apb_ssi specifications version 3.23 onward
define a 32-bits maximum transfer size synthesis parameter
(SSI_MAX_XFER_SIZE=32) in addition to the legacy 16-bits configuration
(SSI_MAX_XFER_SIZE=16) for SPI controllers. When SSI_MAX_XFER_SIZE=32,
the layout of the ctrlr0 register changes, moving the data frame format
field from bits [3..0] to bits [16..20], and the RX/TX FIFO word size
can be up to 32-bits.
To support this new format, introduce the DW SPI capability flag
DW_SPI_CAP_DFS32 to indicate that a controller is configured with
SSI_MAX_XFER_SIZE=32. Since SSI_MAX_XFER_SIZE is a controller synthesis
parameter not accessible through a register, the detection of this
parameter value is done in spi_hw_init() by writing and reading the
ctrlr0 register and testing the value of bits [3..0]. These bits are
ignored (unchanged) for SSI_MAX_XFER_SIZE=16, allowing the detection.
If a DFS32 capable SPI controller is detected, the new field dfs_offset
in struct dw_spi is set to SPI_DFS32_OFFSET (16).
dw_spi_update_config() is modified to set the data frame size field at
the correct position is the CTRLR0 register, as indicated by the
dfs_offset field of the dw_spi structure.
The DW_SPI_CAP_DFS32 flag is also unconditionally set for SPI slave
controllers, e.g. controllers that have the DW_SPI_CAP_DWC_SSI
capability flag set. However, for these ssi controllers, the dfs_offset
field is set to 0 as before (as per specifications).
Finally, for any controller with the DW_SPI_CAP_DFS32 capability flag
set, dw_spi_add_host() extends the value of bits_per_word_mask from
16-bits to 32-bits. dw_reader() and dw_writer() are also modified to
handle 32-bits iTX/RX FIFO words.
Suggested-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20201206011817.11700-3-damien.lemoal@wdc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-06 01:18:16 +00:00
|
|
|
#include <linux/bitfield.h>
|
2009-12-14 22:20:22 +00:00
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
|
2020-05-05 13:06:12 +00:00
|
|
|
#define DW_SPI_CTRLR0 0x00
|
|
|
|
|
#define DW_SPI_CTRLR1 0x04
|
2011-09-20 18:06:17 +00:00
|
|
|
#define DW_SPI_SSIENR 0x08
|
|
|
|
|
#define DW_SPI_MWCR 0x0c
|
|
|
|
|
#define DW_SPI_SER 0x10
|
|
|
|
|
#define DW_SPI_BAUDR 0x14
|
2020-05-05 13:06:12 +00:00
|
|
|
#define DW_SPI_TXFTLR 0x18
|
|
|
|
|
#define DW_SPI_RXFTLR 0x1c
|
2011-09-20 18:06:17 +00:00
|
|
|
#define DW_SPI_TXFLR 0x20
|
|
|
|
|
#define DW_SPI_RXFLR 0x24
|
|
|
|
|
#define DW_SPI_SR 0x28
|
|
|
|
|
#define DW_SPI_IMR 0x2c
|
|
|
|
|
#define DW_SPI_ISR 0x30
|
|
|
|
|
#define DW_SPI_RISR 0x34
|
|
|
|
|
#define DW_SPI_TXOICR 0x38
|
|
|
|
|
#define DW_SPI_RXOICR 0x3c
|
|
|
|
|
#define DW_SPI_RXUICR 0x40
|
|
|
|
|
#define DW_SPI_MSTICR 0x44
|
|
|
|
|
#define DW_SPI_ICR 0x48
|
|
|
|
|
#define DW_SPI_DMACR 0x4c
|
|
|
|
|
#define DW_SPI_DMATDLR 0x50
|
|
|
|
|
#define DW_SPI_DMARDLR 0x54
|
|
|
|
|
#define DW_SPI_IDR 0x58
|
|
|
|
|
#define DW_SPI_VERSION 0x5c
|
|
|
|
|
#define DW_SPI_DR 0x60
|
2020-08-24 20:30:05 +00:00
|
|
|
#define DW_SPI_RX_SAMPLE_DLY 0xf0
|
2018-10-11 11:20:07 +00:00
|
|
|
#define DW_SPI_CS_OVERRIDE 0xf4
|
2011-09-20 18:06:17 +00:00
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
/* Bit fields in CTRLR0 (DWC APB SSI) */
|
|
|
|
|
#define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)
|
2021-11-15 18:19:13 +00:00
|
|
|
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_PSSI_CTRLR0_FRF_MASK GENMASK(5, 4)
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_SPI_CTRLR0_FRF_MOTO_SPI 0x0
|
|
|
|
|
#define DW_SPI_CTRLR0_FRF_TI_SSP 0x1
|
|
|
|
|
#define DW_SPI_CTRLR0_FRF_NS_MICROWIRE 0x2
|
|
|
|
|
#define DW_SPI_CTRLR0_FRF_RESV 0x3
|
|
|
|
|
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_PSSI_CTRLR0_MODE_MASK GENMASK(7, 6)
|
|
|
|
|
#define DW_PSSI_CTRLR0_SCPHA BIT(6)
|
|
|
|
|
#define DW_PSSI_CTRLR0_SCPOL BIT(7)
|
2021-11-15 18:19:13 +00:00
|
|
|
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_PSSI_CTRLR0_TMOD_MASK GENMASK(9, 8)
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_SPI_CTRLR0_TMOD_TR 0x0 /* xmit & recv */
|
|
|
|
|
#define DW_SPI_CTRLR0_TMOD_TO 0x1 /* xmit only */
|
|
|
|
|
#define DW_SPI_CTRLR0_TMOD_RO 0x2 /* recv only */
|
|
|
|
|
#define DW_SPI_CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
|
|
|
|
|
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_PSSI_CTRLR0_SLV_OE BIT(10)
|
|
|
|
|
#define DW_PSSI_CTRLR0_SRL BIT(11)
|
|
|
|
|
#define DW_PSSI_CTRLR0_CFS BIT(12)
|
2021-11-15 18:19:13 +00:00
|
|
|
|
|
|
|
|
/* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_HSSI_CTRLR0_DFS_MASK GENMASK(4, 0)
|
|
|
|
|
#define DW_HSSI_CTRLR0_FRF_MASK GENMASK(7, 6)
|
|
|
|
|
#define DW_HSSI_CTRLR0_SCPHA BIT(8)
|
|
|
|
|
#define DW_HSSI_CTRLR0_SCPOL BIT(9)
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_HSSI_CTRLR0_SRL BIT(13)
|
2020-05-05 13:06:14 +00:00
|
|
|
|
2020-09-20 11:28:54 +00:00
|
|
|
/*
|
|
|
|
|
* For Keem Bay, CTRLR0[31] is used to select controller mode.
|
|
|
|
|
* 0: SSI is slave
|
|
|
|
|
* 1: SSI is master
|
|
|
|
|
*/
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31)
|
2020-09-20 11:28:54 +00:00
|
|
|
|
2020-10-07 23:55:06 +00:00
|
|
|
/* Bit fields in CTRLR1 */
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_SPI_NDF_MASK GENMASK(15, 0)
|
2020-10-07 23:55:06 +00:00
|
|
|
|
2009-12-14 22:20:22 +00:00
|
|
|
/* Bit fields in SR, 7 bits */
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_SPI_SR_MASK GENMASK(6, 0)
|
|
|
|
|
#define DW_SPI_SR_BUSY BIT(0)
|
|
|
|
|
#define DW_SPI_SR_TF_NOT_FULL BIT(1)
|
|
|
|
|
#define DW_SPI_SR_TF_EMPT BIT(2)
|
|
|
|
|
#define DW_SPI_SR_RF_NOT_EMPT BIT(3)
|
|
|
|
|
#define DW_SPI_SR_RF_FULL BIT(4)
|
|
|
|
|
#define DW_SPI_SR_TX_ERR BIT(5)
|
|
|
|
|
#define DW_SPI_SR_DCOL BIT(6)
|
2009-12-14 22:20:22 +00:00
|
|
|
|
|
|
|
|
/* Bit fields in ISR, IMR, RISR, 7 bits */
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_SPI_INT_MASK GENMASK(5, 0)
|
|
|
|
|
#define DW_SPI_INT_TXEI BIT(0)
|
|
|
|
|
#define DW_SPI_INT_TXOI BIT(1)
|
|
|
|
|
#define DW_SPI_INT_RXUI BIT(2)
|
|
|
|
|
#define DW_SPI_INT_RXOI BIT(3)
|
|
|
|
|
#define DW_SPI_INT_RXFI BIT(4)
|
|
|
|
|
#define DW_SPI_INT_MSTI BIT(5)
|
2009-12-14 22:20:22 +00:00
|
|
|
|
2014-10-02 13:31:07 +00:00
|
|
|
/* Bit fields in DMACR */
|
2021-11-15 18:19:14 +00:00
|
|
|
#define DW_SPI_DMACR_RDMAE BIT(0)
|
|
|
|
|
#define DW_SPI_DMACR_TDMAE BIT(1)
|
2014-10-02 13:31:07 +00:00
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
/* Mem/DMA operations helpers */
|
|
|
|
|
#define DW_SPI_WAIT_RETRIES 5
|
|
|
|
|
#define DW_SPI_BUF_SIZE \
|
2020-10-07 23:55:06 +00:00
|
|
|
(sizeof_field(struct spi_mem_op, cmd.opcode) + \
|
|
|
|
|
sizeof_field(struct spi_mem_op, addr.val) + 256)
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_SPI_GET_BYTE(_val, _idx) \
|
2020-10-07 23:55:06 +00:00
|
|
|
((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
|
2020-10-07 23:55:04 +00:00
|
|
|
|
2020-09-20 11:28:53 +00:00
|
|
|
/* DW SPI capabilities */
|
|
|
|
|
#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
|
2020-09-20 11:28:54 +00:00
|
|
|
#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
|
2021-11-15 18:19:13 +00:00
|
|
|
#define DW_SPI_CAP_DWC_HSSI BIT(2)
|
spi: dw: Add support for 32-bits max xfer size
The Synopsis DesignWare DW_apb_ssi specifications version 3.23 onward
define a 32-bits maximum transfer size synthesis parameter
(SSI_MAX_XFER_SIZE=32) in addition to the legacy 16-bits configuration
(SSI_MAX_XFER_SIZE=16) for SPI controllers. When SSI_MAX_XFER_SIZE=32,
the layout of the ctrlr0 register changes, moving the data frame format
field from bits [3..0] to bits [16..20], and the RX/TX FIFO word size
can be up to 32-bits.
To support this new format, introduce the DW SPI capability flag
DW_SPI_CAP_DFS32 to indicate that a controller is configured with
SSI_MAX_XFER_SIZE=32. Since SSI_MAX_XFER_SIZE is a controller synthesis
parameter not accessible through a register, the detection of this
parameter value is done in spi_hw_init() by writing and reading the
ctrlr0 register and testing the value of bits [3..0]. These bits are
ignored (unchanged) for SSI_MAX_XFER_SIZE=16, allowing the detection.
If a DFS32 capable SPI controller is detected, the new field dfs_offset
in struct dw_spi is set to SPI_DFS32_OFFSET (16).
dw_spi_update_config() is modified to set the data frame size field at
the correct position is the CTRLR0 register, as indicated by the
dfs_offset field of the dw_spi structure.
The DW_SPI_CAP_DFS32 flag is also unconditionally set for SPI slave
controllers, e.g. controllers that have the DW_SPI_CAP_DWC_SSI
capability flag set. However, for these ssi controllers, the dfs_offset
field is set to 0 as before (as per specifications).
Finally, for any controller with the DW_SPI_CAP_DFS32 capability flag
set, dw_spi_add_host() extends the value of bits_per_word_mask from
16-bits to 32-bits. dw_reader() and dw_writer() are also modified to
handle 32-bits iTX/RX FIFO words.
Suggested-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20201206011817.11700-3-damien.lemoal@wdc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-06 01:18:16 +00:00
|
|
|
#define DW_SPI_CAP_DFS32 BIT(3)
|
2020-09-20 11:28:53 +00:00
|
|
|
|
2020-10-07 23:54:56 +00:00
|
|
|
/* Slave spi_transfer/spi_mem_op related */
|
|
|
|
|
struct dw_spi_cfg {
|
|
|
|
|
u8 tmode;
|
|
|
|
|
u8 dfs;
|
|
|
|
|
u32 ndf;
|
|
|
|
|
u32 freq;
|
|
|
|
|
};
|
|
|
|
|
|
2010-12-24 05:59:11 +00:00
|
|
|
struct dw_spi;
|
|
|
|
|
struct dw_spi_dma_ops {
|
2020-05-06 15:30:24 +00:00
|
|
|
int (*dma_init)(struct device *dev, struct dw_spi *dws);
|
2010-12-24 05:59:11 +00:00
|
|
|
void (*dma_exit)(struct dw_spi *dws);
|
2015-03-09 14:48:49 +00:00
|
|
|
int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
|
2018-02-01 15:17:29 +00:00
|
|
|
bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
|
2015-03-09 14:48:49 +00:00
|
|
|
struct spi_transfer *xfer);
|
|
|
|
|
int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
|
2015-03-09 14:48:48 +00:00
|
|
|
void (*dma_stop)(struct dw_spi *dws);
|
2010-12-24 05:59:11 +00:00
|
|
|
};
|
|
|
|
|
|
2009-12-14 22:20:22 +00:00
|
|
|
struct dw_spi {
|
2018-02-01 15:17:29 +00:00
|
|
|
struct spi_controller *master;
|
2009-12-14 22:20:22 +00:00
|
|
|
|
|
|
|
|
void __iomem *regs;
|
|
|
|
|
unsigned long paddr;
|
|
|
|
|
int irq;
|
2010-01-20 20:49:45 +00:00
|
|
|
u32 fifo_len; /* depth of the FIFO buffer */
|
spi: dw: Add support for 32-bits max xfer size
The Synopsis DesignWare DW_apb_ssi specifications version 3.23 onward
define a 32-bits maximum transfer size synthesis parameter
(SSI_MAX_XFER_SIZE=32) in addition to the legacy 16-bits configuration
(SSI_MAX_XFER_SIZE=16) for SPI controllers. When SSI_MAX_XFER_SIZE=32,
the layout of the ctrlr0 register changes, moving the data frame format
field from bits [3..0] to bits [16..20], and the RX/TX FIFO word size
can be up to 32-bits.
To support this new format, introduce the DW SPI capability flag
DW_SPI_CAP_DFS32 to indicate that a controller is configured with
SSI_MAX_XFER_SIZE=32. Since SSI_MAX_XFER_SIZE is a controller synthesis
parameter not accessible through a register, the detection of this
parameter value is done in spi_hw_init() by writing and reading the
ctrlr0 register and testing the value of bits [3..0]. These bits are
ignored (unchanged) for SSI_MAX_XFER_SIZE=16, allowing the detection.
If a DFS32 capable SPI controller is detected, the new field dfs_offset
in struct dw_spi is set to SPI_DFS32_OFFSET (16).
dw_spi_update_config() is modified to set the data frame size field at
the correct position is the CTRLR0 register, as indicated by the
dfs_offset field of the dw_spi structure.
The DW_SPI_CAP_DFS32 flag is also unconditionally set for SPI slave
controllers, e.g. controllers that have the DW_SPI_CAP_DWC_SSI
capability flag set. However, for these ssi controllers, the dfs_offset
field is set to 0 as before (as per specifications).
Finally, for any controller with the DW_SPI_CAP_DFS32 capability flag
set, dw_spi_add_host() extends the value of bits_per_word_mask from
16-bits to 32-bits. dw_reader() and dw_writer() are also modified to
handle 32-bits iTX/RX FIFO words.
Suggested-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20201206011817.11700-3-damien.lemoal@wdc.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-06 01:18:16 +00:00
|
|
|
unsigned int dfs_offset; /* CTRLR0 DFS field offset */
|
2020-10-07 23:55:07 +00:00
|
|
|
u32 max_mem_freq; /* max mem-ops bus freq */
|
2009-12-14 22:20:22 +00:00
|
|
|
u32 max_freq; /* max bus freq supported */
|
|
|
|
|
|
2020-09-20 11:28:53 +00:00
|
|
|
u32 caps; /* DW SPI capabilities */
|
|
|
|
|
|
2015-08-18 20:21:53 +00:00
|
|
|
u32 reg_io_width; /* DR I/O width in bytes */
|
2009-12-14 22:20:22 +00:00
|
|
|
u16 bus_num;
|
|
|
|
|
u16 num_cs; /* supported slave numbers */
|
2018-07-17 14:23:11 +00:00
|
|
|
void (*set_cs)(struct spi_device *spi, bool enable);
|
2009-12-14 22:20:22 +00:00
|
|
|
|
|
|
|
|
/* Current message transfer state info */
|
|
|
|
|
void *tx;
|
2020-10-07 23:54:57 +00:00
|
|
|
unsigned int tx_len;
|
2009-12-14 22:20:22 +00:00
|
|
|
void *rx;
|
2020-10-07 23:54:57 +00:00
|
|
|
unsigned int rx_len;
|
2021-11-15 18:19:13 +00:00
|
|
|
u8 buf[DW_SPI_BUF_SIZE];
|
2009-12-14 22:20:22 +00:00
|
|
|
int dma_mapped;
|
|
|
|
|
u8 n_bytes; /* current is a 1/2 bytes op */
|
|
|
|
|
irqreturn_t (*transfer_handler)(struct dw_spi *dws);
|
2016-09-04 00:04:49 +00:00
|
|
|
u32 current_freq; /* frequency in hz */
|
2020-08-24 20:30:05 +00:00
|
|
|
u32 cur_rx_sample_dly;
|
|
|
|
|
u32 def_rx_sample_dly_ns;
|
2009-12-14 22:20:22 +00:00
|
|
|
|
2020-10-07 23:55:06 +00:00
|
|
|
/* Custom memory operations */
|
|
|
|
|
struct spi_controller_mem_ops mem_ops;
|
|
|
|
|
|
2015-03-09 14:48:49 +00:00
|
|
|
/* DMA info */
|
2009-12-14 22:20:22 +00:00
|
|
|
struct dma_chan *txchan;
|
2020-05-29 13:11:56 +00:00
|
|
|
u32 txburst;
|
2009-12-14 22:20:22 +00:00
|
|
|
struct dma_chan *rxchan;
|
2020-05-29 13:11:56 +00:00
|
|
|
u32 rxburst;
|
2020-09-20 11:23:22 +00:00
|
|
|
u32 dma_sg_burst;
|
2014-10-28 16:25:02 +00:00
|
|
|
unsigned long dma_chan_busy;
|
2010-12-24 05:59:11 +00:00
|
|
|
dma_addr_t dma_addr; /* phy address of the Data register */
|
2015-11-28 14:09:38 +00:00
|
|
|
const struct dw_spi_dma_ops *dma_ops;
|
2020-05-29 13:11:52 +00:00
|
|
|
struct completion dma_completion;
|
2009-12-14 22:20:22 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
|
struct dentry *debugfs;
|
2020-05-29 13:12:04 +00:00
|
|
|
struct debugfs_regset32 regset;
|
2009-12-14 22:20:22 +00:00
|
|
|
#endif
|
|
|
|
|
};
|
|
|
|
|
|
2011-09-20 18:06:17 +00:00
|
|
|
static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
|
|
|
|
|
{
|
|
|
|
|
return __raw_readl(dws->regs + offset);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
|
|
|
|
|
{
|
|
|
|
|
__raw_writel(val, dws->regs + offset);
|
|
|
|
|
}
|
|
|
|
|
|
2015-08-18 20:21:53 +00:00
|
|
|
static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
|
|
|
|
|
{
|
|
|
|
|
switch (dws->reg_io_width) {
|
|
|
|
|
case 2:
|
2020-09-20 11:28:51 +00:00
|
|
|
return readw_relaxed(dws->regs + offset);
|
2015-08-18 20:21:53 +00:00
|
|
|
case 4:
|
|
|
|
|
default:
|
2020-09-20 11:28:51 +00:00
|
|
|
return readl_relaxed(dws->regs + offset);
|
2015-08-18 20:21:53 +00:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
|
|
|
|
|
{
|
|
|
|
|
switch (dws->reg_io_width) {
|
|
|
|
|
case 2:
|
2020-09-20 11:28:51 +00:00
|
|
|
writew_relaxed(val, dws->regs + offset);
|
2015-08-18 20:21:53 +00:00
|
|
|
break;
|
|
|
|
|
case 4:
|
|
|
|
|
default:
|
2020-09-20 11:28:51 +00:00
|
|
|
writel_relaxed(val, dws->regs + offset);
|
2015-08-18 20:21:53 +00:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
|
2009-12-14 22:20:22 +00:00
|
|
|
{
|
2011-09-20 18:06:17 +00:00
|
|
|
dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
|
2009-12-14 22:20:22 +00:00
|
|
|
}
|
|
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
|
2009-12-14 22:20:22 +00:00
|
|
|
{
|
2011-09-20 18:06:17 +00:00
|
|
|
dw_writel(dws, DW_SPI_BAUDR, div);
|
2009-12-14 22:20:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Disable IRQ bits */
|
2021-11-15 18:19:13 +00:00
|
|
|
static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
|
2009-12-14 22:20:22 +00:00
|
|
|
{
|
|
|
|
|
u32 new_mask;
|
|
|
|
|
|
2011-09-20 18:06:17 +00:00
|
|
|
new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
|
|
|
|
|
dw_writel(dws, DW_SPI_IMR, new_mask);
|
2009-12-14 22:20:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Enable IRQ bits */
|
2021-11-15 18:19:13 +00:00
|
|
|
static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
|
2009-12-14 22:20:22 +00:00
|
|
|
{
|
|
|
|
|
u32 new_mask;
|
|
|
|
|
|
2011-09-20 18:06:17 +00:00
|
|
|
new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
|
|
|
|
|
dw_writel(dws, DW_SPI_IMR, new_mask);
|
2009-12-14 22:20:22 +00:00
|
|
|
}
|
|
|
|
|
|
2015-03-02 12:58:55 +00:00
|
|
|
/*
|
2020-10-07 23:55:02 +00:00
|
|
|
* This disables the SPI controller, interrupts, clears the interrupts status
|
|
|
|
|
* and CS, then re-enables the controller back. Transmit and receive FIFO
|
|
|
|
|
* buffers are cleared when the device is disabled.
|
2015-03-02 12:58:55 +00:00
|
|
|
*/
|
2021-11-15 18:19:13 +00:00
|
|
|
static inline void dw_spi_reset_chip(struct dw_spi *dws)
|
2015-03-02 12:58:55 +00:00
|
|
|
{
|
2021-11-15 18:19:13 +00:00
|
|
|
dw_spi_enable_chip(dws, 0);
|
|
|
|
|
dw_spi_mask_intr(dws, 0xff);
|
2020-09-20 11:28:49 +00:00
|
|
|
dw_readl(dws, DW_SPI_ICR);
|
2020-10-07 23:55:02 +00:00
|
|
|
dw_writel(dws, DW_SPI_SER, 0);
|
2021-11-15 18:19:13 +00:00
|
|
|
dw_spi_enable_chip(dws, 1);
|
2015-03-02 12:58:55 +00:00
|
|
|
}
|
|
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
|
2015-10-14 20:12:23 +00:00
|
|
|
{
|
2021-11-15 18:19:13 +00:00
|
|
|
dw_spi_enable_chip(dws, 0);
|
|
|
|
|
dw_spi_set_clk(dws, 0);
|
2015-10-14 20:12:23 +00:00
|
|
|
}
|
|
|
|
|
|
2018-07-27 19:53:54 +00:00
|
|
|
extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
|
2020-10-07 23:54:56 +00:00
|
|
|
extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
|
|
|
|
|
struct dw_spi_cfg *cfg);
|
2020-10-07 23:55:05 +00:00
|
|
|
extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
|
2013-12-30 18:30:44 +00:00
|
|
|
extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
|
2009-12-14 22:20:22 +00:00
|
|
|
extern void dw_spi_remove_host(struct dw_spi *dws);
|
|
|
|
|
extern int dw_spi_suspend_host(struct dw_spi *dws);
|
|
|
|
|
extern int dw_spi_resume_host(struct dw_spi *dws);
|
2010-12-24 05:59:11 +00:00
|
|
|
|
2020-05-29 13:11:59 +00:00
|
|
|
#ifdef CONFIG_SPI_DW_DMA
|
|
|
|
|
|
2020-05-29 13:12:02 +00:00
|
|
|
extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
|
|
|
|
|
extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
|
2020-05-29 13:11:59 +00:00
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
2020-05-29 13:12:02 +00:00
|
|
|
static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
|
|
|
|
|
static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
|
2020-05-29 13:11:59 +00:00
|
|
|
|
|
|
|
|
#endif /* !CONFIG_SPI_DW_DMA */
|
2020-05-06 15:30:23 +00:00
|
|
|
|
2021-11-15 18:19:13 +00:00
|
|
|
#endif /* __SPI_DW_H__ */
|
