linux/drivers/phy/amlogic/Makefile

# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_MESON8B_USB2)			+= phy-meson8b-usb2.o
obj-$(CONFIG_PHY_MESON_GXL_USB2)		+= phy-meson-gxl-usb2.o
obj-$(CONFIG_PHY_MESON_G12A_USB2)		+= phy-meson-g12a-usb2.o
obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE)		+= phy-meson-g12a-usb3-pcie.o
obj-$(CONFIG_PHY_MESON_AXG_PCIE)		+= phy-meson-axg-pcie.o
obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG)	+= phy-meson-axg-mipi-pcie-analog.o
obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY)		+= phy-meson-axg-mipi-dphy.o
treewide: Add SPDX license identifier - Makefile/Kconfig Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19 12:07:45 +00:00			`# SPDX-License-Identifier: GPL-2.0-only`
phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver This adds support for the MIPI analog PHY which is also used for PCIE found in the Amlogic AXG SoC Family. MIPI or PCIE selection is done by the #phy-cells, making the mode static and exclusive. For now only PCIE functionality is supported. This PHY will be used to replace the mipi_enable clock gating logic which was mistakenly added in the clock subsystem. This also activates a non documented band gap bit in those registers that allows reliable PCIE clock signal generation on AXG platforms. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> 2020-01-23 23:29:41 +00:00			`obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o`
			`obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o`
			`obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o`
			`obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o`
phy: amlogic: Add Amlogic AXG PCIE PHY Driver This adds support for the PCI PHY found in the Amlogic AXG SoC Family. This will allow to mutualize code in pci-meson.c between AXG and G12A SoC. This PHY also uses and chains an analog PHY, which on AXG platform is needed to have reliable PCIe communication. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> 2020-01-23 23:29:42 +00:00			`obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o`
phy: amlogic: Add Amlogic AXG MIPI/PCIE analog PHY Driver This adds support for the MIPI analog PHY which is also used for PCIE found in the Amlogic AXG SoC Family. MIPI or PCIE selection is done by the #phy-cells, making the mode static and exclusive. For now only PCIE functionality is supported. This PHY will be used to replace the mipi_enable clock gating logic which was mistakenly added in the clock subsystem. This also activates a non documented band gap bit in those registers that allows reliable PCIE clock signal generation on AXG platforms. Signed-off-by: Remi Pommarel <repk@triplefau.lt> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> 2020-01-23 23:29:41 +00:00			`obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o`
phy: amlogic: Add AXG MIPI D-PHY driver The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI panels. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20201116101315.71720-3-narmstrong@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 2020-11-16 10:13:15 +00:00			`obj-$(CONFIG_PHY_MESON_AXG_MIPI_DPHY) += phy-meson-axg-mipi-dphy.o`