2019-02-15 22:39:11 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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2022-01-08 20:35:09 +00:00
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* Copyright 2016-2022 HabanaLabs, Ltd.
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2019-02-15 22:39:11 +00:00
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* All Rights Reserved.
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*/
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2019-04-10 12:18:46 +00:00
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#define pr_fmt(fmt) "habanalabs: " fmt
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2021-07-03 08:50:32 +00:00
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#include <uapi/misc/habanalabs.h>
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2019-02-15 22:39:11 +00:00
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#include "habanalabs.h"
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#include <linux/pci.h>
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2019-02-15 22:39:19 +00:00
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#include <linux/hwmon.h>
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2019-02-15 22:39:11 +00:00
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2022-02-23 12:46:37 +00:00
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#define HL_RESET_DELAY_USEC 10000 /* 10ms */
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2022-03-23 15:11:45 +00:00
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/*
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* hl_set_dram_bar- sets the bar to allow later access to address
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*
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* @hdev: pointer to habanalabs device structure
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* @addr: the address the caller wants to access.
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*
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* @return: the old BAR base address on success, U64_MAX for failure.
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* The caller should set it back to the old address after use.
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*
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* In case the bar space does not cover the whole address space,
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* the bar base address should be set to allow access to a given address.
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* This function can be called also if the bar doesn't need to be set,
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* in that case it just won't change the base.
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*/
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static uint64_t hl_set_dram_bar(struct hl_device *hdev, u64 addr)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 bar_base_addr;
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bar_base_addr = addr & ~(prop->dram_pci_bar_size - 0x1ull);
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return hdev->asic_funcs->set_dram_bar_base(hdev, bar_base_addr);
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}
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static int hl_access_sram_dram_region(struct hl_device *hdev, u64 addr, u64 *val,
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enum debugfs_access_type acc_type, enum pci_region region_type)
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{
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struct pci_mem_region *region = &hdev->pci_mem_region[region_type];
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u64 old_base, rc;
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if (region_type == PCI_REGION_DRAM) {
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old_base = hl_set_dram_bar(hdev, addr);
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if (old_base == U64_MAX)
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return -EIO;
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}
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switch (acc_type) {
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2022-04-05 08:45:51 +00:00
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case DEBUGFS_READ8:
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*val = readb(hdev->pcie_bar[region->bar_id] +
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addr - region->region_base + region->offset_in_bar);
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break;
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case DEBUGFS_WRITE8:
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writeb(*val, hdev->pcie_bar[region->bar_id] +
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addr - region->region_base + region->offset_in_bar);
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break;
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2022-03-23 15:11:45 +00:00
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case DEBUGFS_READ32:
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*val = readl(hdev->pcie_bar[region->bar_id] +
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addr - region->region_base + region->offset_in_bar);
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break;
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case DEBUGFS_WRITE32:
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writel(*val, hdev->pcie_bar[region->bar_id] +
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addr - region->region_base + region->offset_in_bar);
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break;
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case DEBUGFS_READ64:
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*val = readq(hdev->pcie_bar[region->bar_id] +
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addr - region->region_base + region->offset_in_bar);
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break;
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case DEBUGFS_WRITE64:
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writeq(*val, hdev->pcie_bar[region->bar_id] +
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addr - region->region_base + region->offset_in_bar);
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break;
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}
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if (region_type == PCI_REGION_DRAM) {
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rc = hl_set_dram_bar(hdev, old_base);
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if (rc == U64_MAX)
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return -EIO;
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}
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return 0;
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}
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2022-03-24 14:34:49 +00:00
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int hl_dma_map_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct scatterlist *sg;
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int rc, i;
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rc = dma_map_sgtable(&hdev->pdev->dev, sgt, dir, 0);
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if (rc)
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return rc;
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/* Shift to the device's base physical address of host memory if necessary */
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if (prop->device_dma_offset_for_host_access)
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for_each_sgtable_dma_sg(sgt, sg, i)
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sg->dma_address += prop->device_dma_offset_for_host_access;
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return 0;
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}
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void hl_dma_unmap_sgtable(struct hl_device *hdev, struct sg_table *sgt, enum dma_data_direction dir)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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struct scatterlist *sg;
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int i;
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/* Cancel the device's base physical address of host memory if necessary */
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if (prop->device_dma_offset_for_host_access)
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for_each_sgtable_dma_sg(sgt, sg, i)
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sg->dma_address -= prop->device_dma_offset_for_host_access;
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dma_unmap_sgtable(&hdev->pdev->dev, sgt, dir, 0);
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}
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2022-03-23 15:11:45 +00:00
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/*
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* hl_access_cfg_region - access the config region
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*
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* @hdev: pointer to habanalabs device structure
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* @addr: the address to access
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* @val: the value to write from or read to
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* @acc_type: the type of access (read/write 64/32)
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*/
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int hl_access_cfg_region(struct hl_device *hdev, u64 addr, u64 *val,
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enum debugfs_access_type acc_type)
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{
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struct pci_mem_region *cfg_region = &hdev->pci_mem_region[PCI_REGION_CFG];
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u32 val_h, val_l;
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2022-03-16 17:45:24 +00:00
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if (!IS_ALIGNED(addr, sizeof(u32))) {
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dev_err(hdev->dev, "address %#llx not a multiple of %zu\n", addr, sizeof(u32));
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return -EINVAL;
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}
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2022-03-23 15:11:45 +00:00
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switch (acc_type) {
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case DEBUGFS_READ32:
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*val = RREG32(addr - cfg_region->region_base);
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break;
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case DEBUGFS_WRITE32:
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WREG32(addr - cfg_region->region_base, *val);
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break;
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case DEBUGFS_READ64:
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val_l = RREG32(addr - cfg_region->region_base);
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val_h = RREG32(addr + sizeof(u32) - cfg_region->region_base);
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*val = (((u64) val_h) << 32) | val_l;
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break;
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case DEBUGFS_WRITE64:
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WREG32(addr - cfg_region->region_base, lower_32_bits(*val));
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WREG32(addr + sizeof(u32) - cfg_region->region_base, upper_32_bits(*val));
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break;
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2022-04-05 08:45:51 +00:00
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default:
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dev_err(hdev->dev, "access type %d is not supported\n", acc_type);
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return -EOPNOTSUPP;
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2022-03-23 15:11:45 +00:00
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}
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2022-04-05 08:45:51 +00:00
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2022-03-23 15:11:45 +00:00
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return 0;
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}
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/*
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* hl_access_dev_mem - access device memory
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*
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* @hdev: pointer to habanalabs device structure
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* @region: the memory region the address belongs to
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* @region_type: the type of the region the address belongs to
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* @addr: the address to access
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* @val: the value to write from or read to
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* @acc_type: the type of access (r/w, 32/64)
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*/
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int hl_access_dev_mem(struct hl_device *hdev, struct pci_mem_region *region,
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enum pci_region region_type, u64 addr, u64 *val, enum debugfs_access_type acc_type)
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{
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switch (region_type) {
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case PCI_REGION_CFG:
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return hl_access_cfg_region(hdev, addr, val, acc_type);
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case PCI_REGION_SRAM:
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case PCI_REGION_DRAM:
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return hl_access_sram_dram_region(hdev, addr, val, acc_type,
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region_type);
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default:
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return -EFAULT;
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}
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return 0;
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}
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2019-03-24 08:15:44 +00:00
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enum hl_device_status hl_device_status(struct hl_device *hdev)
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{
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enum hl_device_status status;
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2021-11-23 13:15:22 +00:00
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if (hdev->reset_info.in_reset)
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2019-03-24 08:15:44 +00:00
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status = HL_DEVICE_STATUS_IN_RESET;
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2021-11-23 13:15:22 +00:00
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else if (hdev->reset_info.needs_reset)
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2020-10-05 11:40:10 +00:00
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status = HL_DEVICE_STATUS_NEEDS_RESET;
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2020-12-22 13:21:07 +00:00
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else if (hdev->disabled)
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status = HL_DEVICE_STATUS_MALFUNCTION;
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2021-08-16 10:27:12 +00:00
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else if (!hdev->init_done)
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status = HL_DEVICE_STATUS_IN_DEVICE_CREATION;
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2019-03-24 08:15:44 +00:00
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else
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status = HL_DEVICE_STATUS_OPERATIONAL;
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return status;
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2020-01-07 21:44:32 +00:00
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}
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2019-03-24 08:15:44 +00:00
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2020-10-05 11:40:10 +00:00
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bool hl_device_operational(struct hl_device *hdev,
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enum hl_device_status *status)
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{
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enum hl_device_status current_status;
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current_status = hl_device_status(hdev);
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if (status)
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*status = current_status;
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switch (current_status) {
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case HL_DEVICE_STATUS_IN_RESET:
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case HL_DEVICE_STATUS_MALFUNCTION:
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case HL_DEVICE_STATUS_NEEDS_RESET:
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return false;
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case HL_DEVICE_STATUS_OPERATIONAL:
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2021-08-16 10:27:12 +00:00
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case HL_DEVICE_STATUS_IN_DEVICE_CREATION:
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2020-10-05 11:40:10 +00:00
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default:
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return true;
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}
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}
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2019-02-15 22:39:11 +00:00
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static void hpriv_release(struct kref *ref)
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{
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2021-05-20 10:30:31 +00:00
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u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0};
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bool device_is_idle = true;
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2019-02-15 22:39:11 +00:00
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struct hl_fpriv *hpriv;
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struct hl_device *hdev;
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hpriv = container_of(ref, struct hl_fpriv, refcount);
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hdev = hpriv->hdev;
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put_pid(hpriv->taskpid);
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2019-02-15 22:39:24 +00:00
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hl_debugfs_remove_file(hpriv);
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2019-02-15 22:39:21 +00:00
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mutex_destroy(&hpriv->restore_phase_mutex);
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2021-05-20 10:30:31 +00:00
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if ((!hdev->pldm) && (hdev->pdev) &&
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(!hdev->asic_funcs->is_device_idle(hdev,
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idle_mask,
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HL_BUSY_ENGINES_MASK_EXT_SIZE, NULL))) {
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dev_err(hdev->dev,
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"device not idle after user context is closed (0x%llx_%llx)\n",
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idle_mask[1], idle_mask[0]);
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device_is_idle = false;
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}
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2021-09-30 08:22:32 +00:00
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/* We need to remove the user from the list to make sure the reset process won't
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* try to kill the user process. Because, if we got here, it means there are no
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* more driver/device resources that the user process is occupying so there is
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* no need to kill it
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*
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* However, we can't set the compute_ctx to NULL at this stage. This is to prevent
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* a race between the release and opening the device again. We don't want to let
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* a user open the device while there a reset is about to happen.
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*/
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mutex_lock(&hdev->fpriv_list_lock);
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list_del(&hpriv->dev_node);
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mutex_unlock(&hdev->fpriv_list_lock);
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2021-05-20 10:30:31 +00:00
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if ((hdev->reset_if_device_not_idle && !device_is_idle)
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|| hdev->reset_upon_device_release)
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2021-09-16 11:00:38 +00:00
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hl_device_reset(hdev, HL_DRV_RESET_DEV_RELEASE);
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2021-09-30 08:22:32 +00:00
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2021-11-30 21:08:21 +00:00
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/* Now we can mark the compute_ctx as not active. Even if a reset is running in a different
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2021-09-30 08:22:32 +00:00
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* thread, we don't care because the in_reset is marked so if a user will try to open
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2021-11-30 21:08:21 +00:00
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* the device it will fail on that, even if compute_ctx is false.
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2021-09-30 08:22:32 +00:00
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*/
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mutex_lock(&hdev->fpriv_list_lock);
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2021-11-30 21:08:21 +00:00
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hdev->is_compute_ctx_active = false;
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2021-09-30 08:22:32 +00:00
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mutex_unlock(&hdev->fpriv_list_lock);
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2022-02-28 14:08:20 +00:00
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hdev->compute_ctx_in_release = 0;
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2021-09-30 08:22:32 +00:00
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kfree(hpriv);
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2019-02-15 22:39:11 +00:00
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}
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void hl_hpriv_get(struct hl_fpriv *hpriv)
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{
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kref_get(&hpriv->refcount);
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}
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2021-02-18 08:24:02 +00:00
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int hl_hpriv_put(struct hl_fpriv *hpriv)
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2019-02-15 22:39:11 +00:00
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{
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2021-02-18 08:24:02 +00:00
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return kref_put(&hpriv->refcount, hpriv_release);
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2019-02-15 22:39:11 +00:00
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}
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/*
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* hl_device_release - release function for habanalabs device
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*
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* @inode: pointer to inode structure
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* @filp: pointer to file structure
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*
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* Called when process closes an habanalabs device
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*/
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static int hl_device_release(struct inode *inode, struct file *filp)
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{
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struct hl_fpriv *hpriv = filp->private_data;
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2021-02-01 17:44:34 +00:00
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struct hl_device *hdev = hpriv->hdev;
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filp->private_data = NULL;
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if (!hdev) {
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|
|
pr_crit("Closing FD after device was removed. Memory leak will occur and it is advised to reboot.\n");
|
|
|
|
put_pid(hpriv->taskpid);
|
|
|
|
return 0;
|
|
|
|
}
|
2019-02-15 22:39:11 +00:00
|
|
|
|
2021-01-12 16:37:19 +00:00
|
|
|
/* Each pending user interrupt holds the user's context, hence we
|
|
|
|
* must release them all before calling hl_ctx_mgr_fini().
|
|
|
|
*/
|
|
|
|
hl_release_pending_user_interrupts(hpriv->hdev);
|
|
|
|
|
2021-02-10 12:29:33 +00:00
|
|
|
hl_cb_mgr_fini(hdev, &hpriv->cb_mgr);
|
2022-03-20 14:15:01 +00:00
|
|
|
hl_mem_mgr_fini(&hpriv->mem_mgr);
|
2021-02-10 12:29:33 +00:00
|
|
|
hl_ctx_mgr_fini(hdev, &hpriv->ctx_mgr);
|
|
|
|
|
2022-02-28 14:08:20 +00:00
|
|
|
hdev->compute_ctx_in_release = 1;
|
|
|
|
|
2021-02-18 08:24:02 +00:00
|
|
|
if (!hl_hpriv_put(hpriv))
|
2021-07-13 05:11:54 +00:00
|
|
|
dev_notice(hdev->dev,
|
|
|
|
"User process closed FD but device still in use\n");
|
2019-02-15 22:39:11 +00:00
|
|
|
|
2021-05-24 08:25:21 +00:00
|
|
|
hdev->last_open_session_duration_jif =
|
|
|
|
jiffies - hdev->last_successful_open_jif;
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-07-30 06:10:50 +00:00
|
|
|
static int hl_device_release_ctrl(struct inode *inode, struct file *filp)
|
|
|
|
{
|
|
|
|
struct hl_fpriv *hpriv = filp->private_data;
|
2021-02-01 17:44:34 +00:00
|
|
|
struct hl_device *hdev = hpriv->hdev;
|
2019-07-30 06:10:50 +00:00
|
|
|
|
|
|
|
filp->private_data = NULL;
|
|
|
|
|
2021-02-01 17:44:34 +00:00
|
|
|
if (!hdev) {
|
|
|
|
pr_err("Closing FD after device was removed\n");
|
|
|
|
goto out;
|
|
|
|
}
|
2019-07-30 06:10:50 +00:00
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_lock(&hdev->fpriv_ctrl_list_lock);
|
2019-07-30 06:10:50 +00:00
|
|
|
list_del(&hpriv->dev_node);
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_unlock(&hdev->fpriv_ctrl_list_lock);
|
2021-02-01 17:44:34 +00:00
|
|
|
out:
|
2021-02-19 12:05:33 +00:00
|
|
|
put_pid(hpriv->taskpid);
|
|
|
|
|
2019-07-30 06:10:50 +00:00
|
|
|
kfree(hpriv);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:15 +00:00
|
|
|
/*
|
|
|
|
* hl_mmap - mmap function for habanalabs device
|
|
|
|
*
|
|
|
|
* @*filp: pointer to file structure
|
|
|
|
* @*vma: pointer to vm_area_struct of the process
|
|
|
|
*
|
|
|
|
* Called when process does an mmap on habanalabs device. Call the device's mmap
|
|
|
|
* function at the end of the common code.
|
|
|
|
*/
|
|
|
|
static int hl_mmap(struct file *filp, struct vm_area_struct *vma)
|
|
|
|
{
|
|
|
|
struct hl_fpriv *hpriv = filp->private_data;
|
2021-02-01 17:44:34 +00:00
|
|
|
struct hl_device *hdev = hpriv->hdev;
|
2020-08-29 08:51:39 +00:00
|
|
|
unsigned long vm_pgoff;
|
2019-02-15 22:39:15 +00:00
|
|
|
|
2021-02-01 17:44:34 +00:00
|
|
|
if (!hdev) {
|
|
|
|
pr_err_ratelimited("Trying to mmap after device was removed! Please close FD\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
2020-08-29 08:51:39 +00:00
|
|
|
vm_pgoff = vma->vm_pgoff;
|
|
|
|
vma->vm_pgoff = HL_MMAP_OFFSET_VALUE_GET(vm_pgoff);
|
|
|
|
|
|
|
|
switch (vm_pgoff & HL_MMAP_TYPE_MASK) {
|
|
|
|
case HL_MMAP_TYPE_CB:
|
2019-02-15 22:39:15 +00:00
|
|
|
return hl_cb_mmap(hpriv, vma);
|
2021-01-05 10:55:06 +00:00
|
|
|
|
|
|
|
case HL_MMAP_TYPE_BLOCK:
|
|
|
|
return hl_hw_block_mmap(hpriv, vma);
|
2021-12-23 11:24:34 +00:00
|
|
|
|
|
|
|
case HL_MMAP_TYPE_TS_BUFF:
|
2022-03-20 14:15:01 +00:00
|
|
|
return hl_mem_mgr_mmap(&hpriv->mem_mgr, vma, NULL);
|
2019-02-15 22:39:15 +00:00
|
|
|
}
|
|
|
|
|
2019-02-27 10:15:16 +00:00
|
|
|
return -EINVAL;
|
2019-02-15 22:39:15 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
static const struct file_operations hl_ops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = hl_device_open,
|
2019-02-15 22:39:15 +00:00
|
|
|
.release = hl_device_release,
|
|
|
|
.mmap = hl_mmap,
|
|
|
|
.unlocked_ioctl = hl_ioctl,
|
|
|
|
.compat_ioctl = hl_ioctl
|
2019-02-15 22:39:11 +00:00
|
|
|
};
|
|
|
|
|
2019-07-30 06:10:50 +00:00
|
|
|
static const struct file_operations hl_ctrl_ops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = hl_device_open_ctrl,
|
|
|
|
.release = hl_device_release_ctrl,
|
|
|
|
.unlocked_ioctl = hl_ioctl_control,
|
|
|
|
.compat_ioctl = hl_ioctl_control
|
|
|
|
};
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
static void device_release_func(struct device *dev)
|
|
|
|
{
|
|
|
|
kfree(dev);
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/*
|
2019-08-08 12:25:52 +00:00
|
|
|
* device_init_cdev - Initialize cdev and device for habanalabs device
|
2019-02-15 22:39:11 +00:00
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
* @hclass: pointer to the class object of the device
|
|
|
|
* @minor: minor number of the specific device
|
2019-07-30 06:10:02 +00:00
|
|
|
* @fpos: file operations to install for this device
|
|
|
|
* @name: name of the device as it will appear in the filesystem
|
2019-08-08 12:25:52 +00:00
|
|
|
* @cdev: pointer to the char device object that will be initialized
|
|
|
|
* @dev: pointer to the device object that will be initialized
|
2019-02-15 22:39:11 +00:00
|
|
|
*
|
2019-08-08 12:25:52 +00:00
|
|
|
* Initialize a cdev and a Linux device for habanalabs's device.
|
2019-02-15 22:39:11 +00:00
|
|
|
*/
|
2019-08-08 12:25:52 +00:00
|
|
|
static int device_init_cdev(struct hl_device *hdev, struct class *hclass,
|
2019-07-30 06:10:02 +00:00
|
|
|
int minor, const struct file_operations *fops,
|
|
|
|
char *name, struct cdev *cdev,
|
|
|
|
struct device **dev)
|
2019-02-15 22:39:11 +00:00
|
|
|
{
|
2019-07-30 06:10:02 +00:00
|
|
|
cdev_init(cdev, fops);
|
|
|
|
cdev->owner = THIS_MODULE;
|
2019-08-08 12:25:52 +00:00
|
|
|
|
|
|
|
*dev = kzalloc(sizeof(**dev), GFP_KERNEL);
|
|
|
|
if (!*dev)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
device_initialize(*dev);
|
|
|
|
(*dev)->devt = MKDEV(hdev->major, minor);
|
|
|
|
(*dev)->class = hclass;
|
|
|
|
(*dev)->release = device_release_func;
|
|
|
|
dev_set_drvdata(*dev, hdev);
|
|
|
|
dev_set_name(*dev, "%s", name);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int device_cdev_sysfs_add(struct hl_device *hdev)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = cdev_device_add(&hdev->cdev, hdev->dev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"failed to add a char device to the system\n");
|
|
|
|
return rc;
|
2019-02-15 22:39:11 +00:00
|
|
|
}
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
rc = cdev_device_add(&hdev->cdev_ctrl, hdev->dev_ctrl);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"failed to add a control char device to the system\n");
|
|
|
|
goto delete_cdev_device;
|
2019-02-15 22:39:11 +00:00
|
|
|
}
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
/* hl_sysfs_init() must be done after adding the device to the system */
|
|
|
|
rc = hl_sysfs_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "failed to initialize sysfs\n");
|
|
|
|
goto delete_ctrl_cdev_device;
|
|
|
|
}
|
|
|
|
|
|
|
|
hdev->cdev_sysfs_created = true;
|
2019-02-15 22:39:11 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
delete_ctrl_cdev_device:
|
|
|
|
cdev_device_del(&hdev->cdev_ctrl, hdev->dev_ctrl);
|
|
|
|
delete_cdev_device:
|
|
|
|
cdev_device_del(&hdev->cdev, hdev->dev);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void device_cdev_sysfs_del(struct hl_device *hdev)
|
|
|
|
{
|
2020-11-29 07:34:12 +00:00
|
|
|
if (!hdev->cdev_sysfs_created)
|
|
|
|
goto put_devices;
|
2019-08-08 12:25:52 +00:00
|
|
|
|
|
|
|
hl_sysfs_fini(hdev);
|
|
|
|
cdev_device_del(&hdev->cdev_ctrl, hdev->dev_ctrl);
|
|
|
|
cdev_device_del(&hdev->cdev, hdev->dev);
|
2020-11-29 07:34:12 +00:00
|
|
|
|
|
|
|
put_devices:
|
|
|
|
put_device(hdev->dev);
|
|
|
|
put_device(hdev->dev_ctrl);
|
2019-02-15 22:39:11 +00:00
|
|
|
}
|
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
static void device_hard_reset_pending(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct hl_device_reset_work *device_reset_work =
|
2021-11-22 10:29:22 +00:00
|
|
|
container_of(work, struct hl_device_reset_work, reset_work.work);
|
2020-10-08 07:27:42 +00:00
|
|
|
struct hl_device *hdev = device_reset_work->hdev;
|
2021-08-09 19:43:37 +00:00
|
|
|
u32 flags;
|
2020-10-08 07:27:42 +00:00
|
|
|
int rc;
|
|
|
|
|
2021-11-22 10:29:22 +00:00
|
|
|
flags = device_reset_work->flags | HL_DRV_RESET_FROM_RESET_THR;
|
2021-08-09 19:43:37 +00:00
|
|
|
|
|
|
|
rc = hl_device_reset(hdev, flags);
|
2020-10-08 07:27:42 +00:00
|
|
|
if ((rc == -EBUSY) && !hdev->device_fini_pending) {
|
|
|
|
dev_info(hdev->dev,
|
|
|
|
"Could not reset device. will try again in %u seconds",
|
|
|
|
HL_PENDING_RESET_PER_SEC);
|
|
|
|
|
|
|
|
queue_delayed_work(device_reset_work->wq,
|
|
|
|
&device_reset_work->reset_work,
|
|
|
|
msecs_to_jiffies(HL_PENDING_RESET_PER_SEC * 1000));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/*
|
|
|
|
* device_early_init - do some early initialization for the habanalabs device
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
* Install the relevant function pointers and call the early_init function,
|
|
|
|
* if such a function exists
|
|
|
|
*/
|
|
|
|
static int device_early_init(struct hl_device *hdev)
|
|
|
|
{
|
2020-07-05 10:35:51 +00:00
|
|
|
int i, rc;
|
|
|
|
char workq_name[32];
|
2019-02-15 22:39:13 +00:00
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
switch (hdev->asic_type) {
|
|
|
|
case ASIC_GOYA:
|
2019-02-15 22:39:13 +00:00
|
|
|
goya_set_asic_funcs(hdev);
|
2021-04-03 13:37:29 +00:00
|
|
|
strscpy(hdev->asic_name, "GOYA", sizeof(hdev->asic_name));
|
2019-02-15 22:39:11 +00:00
|
|
|
break;
|
2020-05-11 07:47:05 +00:00
|
|
|
case ASIC_GAUDI:
|
|
|
|
gaudi_set_asic_funcs(hdev);
|
2021-04-03 13:37:29 +00:00
|
|
|
strscpy(hdev->asic_name, "GAUDI", sizeof(hdev->asic_name));
|
2020-05-11 07:47:05 +00:00
|
|
|
break;
|
2021-04-01 10:43:40 +00:00
|
|
|
case ASIC_GAUDI_SEC:
|
|
|
|
gaudi_set_asic_funcs(hdev);
|
|
|
|
strscpy(hdev->asic_name, "GAUDI SEC", sizeof(hdev->asic_name));
|
|
|
|
break;
|
2019-02-15 22:39:11 +00:00
|
|
|
default:
|
|
|
|
dev_err(hdev->dev, "Unrecognized ASIC type %d\n",
|
|
|
|
hdev->asic_type);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
rc = hdev->asic_funcs->early_init(hdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2019-02-15 22:39:14 +00:00
|
|
|
rc = hl_asid_init(hdev);
|
|
|
|
if (rc)
|
|
|
|
goto early_fini;
|
|
|
|
|
2020-07-05 10:35:51 +00:00
|
|
|
if (hdev->asic_prop.completion_queues_count) {
|
|
|
|
hdev->cq_wq = kcalloc(hdev->asic_prop.completion_queues_count,
|
|
|
|
sizeof(*hdev->cq_wq),
|
2021-02-14 13:35:56 +00:00
|
|
|
GFP_KERNEL);
|
2020-07-05 10:35:51 +00:00
|
|
|
if (!hdev->cq_wq) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto asid_fini;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++) {
|
2020-08-12 07:15:27 +00:00
|
|
|
snprintf(workq_name, 32, "hl-free-jobs-%u", (u32) i);
|
2020-07-05 10:35:51 +00:00
|
|
|
hdev->cq_wq[i] = create_singlethread_workqueue(workq_name);
|
2020-07-30 08:20:22 +00:00
|
|
|
if (hdev->cq_wq[i] == NULL) {
|
2020-07-05 10:35:51 +00:00
|
|
|
dev_err(hdev->dev, "Failed to allocate CQ workqueue\n");
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto free_cq_wq;
|
|
|
|
}
|
2019-02-15 22:39:17 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:18 +00:00
|
|
|
hdev->eq_wq = alloc_workqueue("hl-events", WQ_UNBOUND, 0);
|
|
|
|
if (hdev->eq_wq == NULL) {
|
|
|
|
dev_err(hdev->dev, "Failed to allocate EQ workqueue\n");
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto free_cq_wq;
|
|
|
|
}
|
|
|
|
|
2021-12-23 11:24:34 +00:00
|
|
|
hdev->ts_free_obj_wq = alloc_workqueue("hl-ts-free-obj", WQ_UNBOUND, 0);
|
|
|
|
if (!hdev->ts_free_obj_wq) {
|
2021-03-18 15:36:57 +00:00
|
|
|
dev_err(hdev->dev,
|
2021-12-23 11:24:34 +00:00
|
|
|
"Failed to allocate Timestamp registration free workqueue\n");
|
2021-03-18 15:36:57 +00:00
|
|
|
rc = -ENOMEM;
|
|
|
|
goto free_eq_wq;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
hdev->hl_chip_info = kzalloc(sizeof(struct hwmon_chip_info),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!hdev->hl_chip_info) {
|
|
|
|
rc = -ENOMEM;
|
2021-12-23 11:24:34 +00:00
|
|
|
goto free_ts_free_wq;
|
2019-02-15 22:39:19 +00:00
|
|
|
}
|
|
|
|
|
2020-08-12 10:33:44 +00:00
|
|
|
rc = hl_mmu_if_set_funcs(hdev);
|
|
|
|
if (rc)
|
2021-02-23 19:31:27 +00:00
|
|
|
goto free_chip_info;
|
2020-08-12 10:33:44 +00:00
|
|
|
|
2019-02-15 22:39:15 +00:00
|
|
|
hl_cb_mgr_init(&hdev->kernel_cb_mgr);
|
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
hdev->device_reset_work.wq =
|
|
|
|
create_singlethread_workqueue("hl_device_reset");
|
|
|
|
if (!hdev->device_reset_work.wq) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
dev_err(hdev->dev, "Failed to create device reset WQ\n");
|
|
|
|
goto free_cb_mgr;
|
|
|
|
}
|
|
|
|
|
|
|
|
INIT_DELAYED_WORK(&hdev->device_reset_work.reset_work,
|
|
|
|
device_hard_reset_pending);
|
|
|
|
hdev->device_reset_work.hdev = hdev;
|
|
|
|
hdev->device_fini_pending = 0;
|
|
|
|
|
2019-02-15 22:39:17 +00:00
|
|
|
mutex_init(&hdev->send_cpu_message_lock);
|
2019-05-04 14:36:06 +00:00
|
|
|
mutex_init(&hdev->debug_lock);
|
2020-10-30 09:16:23 +00:00
|
|
|
INIT_LIST_HEAD(&hdev->cs_mirror_list);
|
|
|
|
spin_lock_init(&hdev->cs_mirror_lock);
|
2021-11-23 13:15:22 +00:00
|
|
|
spin_lock_init(&hdev->reset_info.lock);
|
2019-07-30 08:56:09 +00:00
|
|
|
INIT_LIST_HEAD(&hdev->fpriv_list);
|
2021-12-08 07:52:03 +00:00
|
|
|
INIT_LIST_HEAD(&hdev->fpriv_ctrl_list);
|
2019-07-30 08:56:09 +00:00
|
|
|
mutex_init(&hdev->fpriv_list_lock);
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_init(&hdev->fpriv_ctrl_list_lock);
|
2021-10-25 06:47:04 +00:00
|
|
|
mutex_init(&hdev->clk_throttling.lock);
|
2019-02-15 22:39:14 +00:00
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
return 0;
|
2019-02-15 22:39:14 +00:00
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
free_cb_mgr:
|
|
|
|
hl_cb_mgr_fini(hdev, &hdev->kernel_cb_mgr);
|
2019-08-28 14:32:04 +00:00
|
|
|
free_chip_info:
|
|
|
|
kfree(hdev->hl_chip_info);
|
2021-12-23 11:24:34 +00:00
|
|
|
free_ts_free_wq:
|
|
|
|
destroy_workqueue(hdev->ts_free_obj_wq);
|
2019-02-15 22:39:19 +00:00
|
|
|
free_eq_wq:
|
|
|
|
destroy_workqueue(hdev->eq_wq);
|
2019-02-15 22:39:18 +00:00
|
|
|
free_cq_wq:
|
2020-07-05 10:35:51 +00:00
|
|
|
for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
|
|
|
|
if (hdev->cq_wq[i])
|
|
|
|
destroy_workqueue(hdev->cq_wq[i]);
|
|
|
|
kfree(hdev->cq_wq);
|
2019-02-15 22:39:17 +00:00
|
|
|
asid_fini:
|
|
|
|
hl_asid_fini(hdev);
|
2019-02-15 22:39:14 +00:00
|
|
|
early_fini:
|
|
|
|
if (hdev->asic_funcs->early_fini)
|
|
|
|
hdev->asic_funcs->early_fini(hdev);
|
|
|
|
|
|
|
|
return rc;
|
2019-02-15 22:39:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* device_early_fini - finalize all that was done in device_early_init
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static void device_early_fini(struct hl_device *hdev)
|
|
|
|
{
|
2020-07-05 10:35:51 +00:00
|
|
|
int i;
|
|
|
|
|
2019-05-04 14:36:06 +00:00
|
|
|
mutex_destroy(&hdev->debug_lock);
|
2019-02-15 22:39:17 +00:00
|
|
|
mutex_destroy(&hdev->send_cpu_message_lock);
|
2019-02-15 22:39:13 +00:00
|
|
|
|
2019-07-30 08:56:09 +00:00
|
|
|
mutex_destroy(&hdev->fpriv_list_lock);
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_destroy(&hdev->fpriv_ctrl_list_lock);
|
2019-07-30 08:56:09 +00:00
|
|
|
|
2021-10-25 06:47:04 +00:00
|
|
|
mutex_destroy(&hdev->clk_throttling.lock);
|
|
|
|
|
2019-02-15 22:39:15 +00:00
|
|
|
hl_cb_mgr_fini(hdev, &hdev->kernel_cb_mgr);
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
kfree(hdev->hl_chip_info);
|
|
|
|
|
2021-12-23 11:24:34 +00:00
|
|
|
destroy_workqueue(hdev->ts_free_obj_wq);
|
2019-02-15 22:39:18 +00:00
|
|
|
destroy_workqueue(hdev->eq_wq);
|
2020-10-08 07:27:42 +00:00
|
|
|
destroy_workqueue(hdev->device_reset_work.wq);
|
2020-07-05 10:35:51 +00:00
|
|
|
|
|
|
|
for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
|
|
|
|
destroy_workqueue(hdev->cq_wq[i]);
|
|
|
|
kfree(hdev->cq_wq);
|
2019-02-15 22:39:17 +00:00
|
|
|
|
2019-02-15 22:39:14 +00:00
|
|
|
hl_asid_fini(hdev);
|
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
if (hdev->asic_funcs->early_fini)
|
|
|
|
hdev->asic_funcs->early_fini(hdev);
|
2019-02-15 22:39:11 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
static void hl_device_heartbeat(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct hl_device *hdev = container_of(work, struct hl_device,
|
|
|
|
work_heartbeat.work);
|
|
|
|
|
2020-10-05 11:40:10 +00:00
|
|
|
if (!hl_device_operational(hdev, NULL))
|
2019-02-15 22:39:20 +00:00
|
|
|
goto reschedule;
|
|
|
|
|
|
|
|
if (!hdev->asic_funcs->send_heartbeat(hdev))
|
|
|
|
goto reschedule;
|
|
|
|
|
2021-11-13 15:58:43 +00:00
|
|
|
if (hl_device_operational(hdev, NULL))
|
|
|
|
dev_err(hdev->dev, "Device heartbeat failed!\n");
|
|
|
|
|
2021-09-16 11:00:38 +00:00
|
|
|
hl_device_reset(hdev, HL_DRV_RESET_HARD | HL_DRV_RESET_HEARTBEAT);
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
reschedule:
|
2021-06-21 06:57:19 +00:00
|
|
|
/*
|
|
|
|
* prev_reset_trigger tracks consecutive fatal h/w errors until first
|
|
|
|
* heartbeat immediately post reset.
|
|
|
|
* If control reached here, then at least one heartbeat work has been
|
|
|
|
* scheduled since last reset/init cycle.
|
|
|
|
* So if the device is not already in reset cycle, reset the flag
|
2021-09-16 11:00:38 +00:00
|
|
|
* prev_reset_trigger as no reset occurred with HL_DRV_RESET_FW_FATAL_ERR
|
2021-06-21 06:57:19 +00:00
|
|
|
* status for at least one heartbeat. From this point driver restarts
|
|
|
|
* tracking future consecutive fatal errors.
|
|
|
|
*/
|
2021-11-23 13:15:22 +00:00
|
|
|
if (!hdev->reset_info.in_reset)
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.prev_reset_trigger = HL_RESET_TRIGGER_DEFAULT;
|
2021-06-21 06:57:19 +00:00
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
schedule_delayed_work(&hdev->work_heartbeat,
|
|
|
|
usecs_to_jiffies(HL_HEARTBEAT_PER_USEC));
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
/*
|
|
|
|
* device_late_init - do late stuff initialization for the habanalabs device
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
* Do stuff that either needs the device H/W queues to be active or needs
|
|
|
|
* to happen after all the rest of the initialization is finished
|
|
|
|
*/
|
|
|
|
static int device_late_init(struct hl_device *hdev)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
2019-05-29 11:24:51 +00:00
|
|
|
if (hdev->asic_funcs->late_init) {
|
|
|
|
rc = hdev->asic_funcs->late_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"failed late initialization for the H/W\n");
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
hdev->high_pll = hdev->asic_prop.high_pll;
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
if (hdev->heartbeat) {
|
|
|
|
INIT_DELAYED_WORK(&hdev->work_heartbeat, hl_device_heartbeat);
|
|
|
|
schedule_delayed_work(&hdev->work_heartbeat,
|
|
|
|
usecs_to_jiffies(HL_HEARTBEAT_PER_USEC));
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
hdev->late_init_done = true;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* device_late_fini - finalize all that was done in device_late_init
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
static void device_late_fini(struct hl_device *hdev)
|
|
|
|
{
|
|
|
|
if (!hdev->late_init_done)
|
|
|
|
return;
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
if (hdev->heartbeat)
|
|
|
|
cancel_delayed_work_sync(&hdev->work_heartbeat);
|
2019-02-15 22:39:19 +00:00
|
|
|
|
|
|
|
if (hdev->asic_funcs->late_fini)
|
|
|
|
hdev->asic_funcs->late_fini(hdev);
|
|
|
|
|
|
|
|
hdev->late_init_done = false;
|
|
|
|
}
|
|
|
|
|
2021-02-23 19:31:27 +00:00
|
|
|
int hl_device_utilization(struct hl_device *hdev, u32 *utilization)
|
2019-08-28 14:32:04 +00:00
|
|
|
{
|
2021-02-23 19:31:27 +00:00
|
|
|
u64 max_power, curr_power, dc_power, dividend;
|
|
|
|
int rc;
|
2019-08-28 14:32:04 +00:00
|
|
|
|
2022-01-17 22:21:49 +00:00
|
|
|
max_power = hdev->max_power;
|
2021-02-23 19:31:27 +00:00
|
|
|
dc_power = hdev->asic_prop.dc_power_default;
|
|
|
|
rc = hl_fw_cpucp_power_get(hdev, &curr_power);
|
2019-08-28 14:32:04 +00:00
|
|
|
|
2021-02-23 19:31:27 +00:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
2019-08-28 14:32:04 +00:00
|
|
|
|
2021-02-23 19:31:27 +00:00
|
|
|
curr_power = clamp(curr_power, dc_power, max_power);
|
2019-08-28 14:32:04 +00:00
|
|
|
|
2021-02-23 19:31:27 +00:00
|
|
|
dividend = (curr_power - dc_power) * 100;
|
|
|
|
*utilization = (u32) div_u64(dividend, (max_power - dc_power));
|
2019-08-28 14:32:04 +00:00
|
|
|
|
2021-02-23 19:31:27 +00:00
|
|
|
return 0;
|
2019-08-28 14:32:04 +00:00
|
|
|
}
|
|
|
|
|
2021-11-30 20:32:13 +00:00
|
|
|
int hl_device_set_debug_mode(struct hl_device *hdev, struct hl_ctx *ctx, bool enable)
|
2019-05-04 14:36:06 +00:00
|
|
|
{
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
mutex_lock(&hdev->debug_lock);
|
|
|
|
|
|
|
|
if (!enable) {
|
|
|
|
if (!hdev->in_debug) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed to disable debug mode because device was not in debug mode\n");
|
|
|
|
rc = -EFAULT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
if (!hdev->reset_info.hard_reset_pending)
|
2021-11-30 20:32:13 +00:00
|
|
|
hdev->asic_funcs->halt_coresight(hdev, ctx);
|
2020-01-05 09:05:45 +00:00
|
|
|
|
2019-05-04 14:36:06 +00:00
|
|
|
hdev->in_debug = 0;
|
|
|
|
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hdev->in_debug) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed to enable debug mode because device is already in debug mode\n");
|
|
|
|
rc = -EFAULT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
hdev->in_debug = 1;
|
|
|
|
|
|
|
|
out:
|
|
|
|
mutex_unlock(&hdev->debug_lock);
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2021-07-06 17:50:33 +00:00
|
|
|
static void take_release_locks(struct hl_device *hdev)
|
|
|
|
{
|
|
|
|
/* Flush anyone that is inside the critical section of enqueue
|
|
|
|
* jobs to the H/W
|
|
|
|
*/
|
|
|
|
hdev->asic_funcs->hw_queues_lock(hdev);
|
|
|
|
hdev->asic_funcs->hw_queues_unlock(hdev);
|
|
|
|
|
|
|
|
/* Flush processes that are sending message to CPU */
|
|
|
|
mutex_lock(&hdev->send_cpu_message_lock);
|
|
|
|
mutex_unlock(&hdev->send_cpu_message_lock);
|
|
|
|
|
|
|
|
/* Flush anyone that is inside device open */
|
|
|
|
mutex_lock(&hdev->fpriv_list_lock);
|
|
|
|
mutex_unlock(&hdev->fpriv_list_lock);
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_lock(&hdev->fpriv_ctrl_list_lock);
|
|
|
|
mutex_unlock(&hdev->fpriv_ctrl_list_lock);
|
2021-07-06 17:50:33 +00:00
|
|
|
}
|
|
|
|
|
2022-02-17 14:15:26 +00:00
|
|
|
static void cleanup_resources(struct hl_device *hdev, bool hard_reset, bool fw_reset,
|
|
|
|
bool skip_wq_flush)
|
2021-07-06 17:50:33 +00:00
|
|
|
{
|
|
|
|
if (hard_reset)
|
|
|
|
device_late_fini(hdev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Halt the engines and disable interrupts so we won't get any more
|
|
|
|
* completions from H/W and we won't have any accesses from the
|
|
|
|
* H/W to the host machine
|
|
|
|
*/
|
2021-08-09 19:43:37 +00:00
|
|
|
hdev->asic_funcs->halt_engines(hdev, hard_reset, fw_reset);
|
2021-07-06 17:50:33 +00:00
|
|
|
|
|
|
|
/* Go over all the queues, release all CS and their jobs */
|
2022-02-17 14:15:26 +00:00
|
|
|
hl_cs_rollback_all(hdev, skip_wq_flush);
|
2021-07-06 17:50:33 +00:00
|
|
|
|
|
|
|
/* Release all pending user interrupts, each pending user interrupt
|
|
|
|
* holds a reference to user context
|
|
|
|
*/
|
|
|
|
hl_release_pending_user_interrupts(hdev);
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/*
|
|
|
|
* hl_device_suspend - initiate device suspend
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
* Puts the hw in the suspend state (all asics).
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
* Called at driver suspend.
|
|
|
|
*/
|
|
|
|
int hl_device_suspend(struct hl_device *hdev)
|
|
|
|
{
|
2019-02-15 22:39:13 +00:00
|
|
|
int rc;
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
pci_save_state(hdev->pdev);
|
|
|
|
|
2019-03-03 20:29:20 +00:00
|
|
|
/* Block future CS/VM/JOB completion operations */
|
2021-11-23 13:15:22 +00:00
|
|
|
spin_lock(&hdev->reset_info.lock);
|
|
|
|
if (hdev->reset_info.in_reset) {
|
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
2019-03-03 20:29:20 +00:00
|
|
|
dev_err(hdev->dev, "Can't suspend while in reset\n");
|
|
|
|
return -EIO;
|
|
|
|
}
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.in_reset = 1;
|
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
2019-03-03 20:29:20 +00:00
|
|
|
|
|
|
|
/* This blocks all other stuff that is not blocked by in_reset */
|
|
|
|
hdev->disabled = true;
|
|
|
|
|
2021-07-06 17:50:33 +00:00
|
|
|
take_release_locks(hdev);
|
2019-03-03 20:29:20 +00:00
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
rc = hdev->asic_funcs->suspend(hdev);
|
|
|
|
if (rc)
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed to disable PCI access of device CPU\n");
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/* Shut down the device */
|
|
|
|
pci_disable_device(hdev->pdev);
|
|
|
|
pci_set_power_state(hdev->pdev, PCI_D3hot);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_device_resume - initiate device resume
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
* Bring the hw back to operating state (all asics).
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
* Called at driver resume.
|
|
|
|
*/
|
|
|
|
int hl_device_resume(struct hl_device *hdev)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
pci_set_power_state(hdev->pdev, PCI_D0);
|
|
|
|
pci_restore_state(hdev->pdev);
|
2019-03-03 20:29:20 +00:00
|
|
|
rc = pci_enable_device_mem(hdev->pdev);
|
2019-02-15 22:39:11 +00:00
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed to enable PCI device in resume\n");
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2019-03-03 20:29:20 +00:00
|
|
|
pci_set_master(hdev->pdev);
|
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
rc = hdev->asic_funcs->resume(hdev);
|
|
|
|
if (rc) {
|
2019-03-03 20:29:20 +00:00
|
|
|
dev_err(hdev->dev, "Failed to resume device after suspend\n");
|
|
|
|
goto disable_device;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
/* 'in_reset' was set to true during suspend, now we must clear it in order
|
|
|
|
* for hard reset to be performed
|
|
|
|
*/
|
|
|
|
hdev->reset_info.in_reset = 0;
|
2019-03-03 20:29:20 +00:00
|
|
|
|
2021-09-16 11:00:38 +00:00
|
|
|
rc = hl_device_reset(hdev, HL_DRV_RESET_HARD);
|
2019-03-03 20:29:20 +00:00
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "Failed to reset device during resume\n");
|
|
|
|
goto disable_device;
|
2019-02-15 22:39:13 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
return 0;
|
2019-03-03 20:29:20 +00:00
|
|
|
|
|
|
|
disable_device:
|
|
|
|
pci_clear_master(hdev->pdev);
|
|
|
|
pci_disable_device(hdev->pdev);
|
|
|
|
|
|
|
|
return rc;
|
2019-02-15 22:39:11 +00:00
|
|
|
}
|
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
static int device_kill_open_processes(struct hl_device *hdev, u32 timeout, bool control_dev)
|
2019-02-15 22:39:20 +00:00
|
|
|
{
|
|
|
|
struct task_struct *task = NULL;
|
2021-12-08 07:52:03 +00:00
|
|
|
struct list_head *fd_list;
|
|
|
|
struct hl_fpriv *hpriv;
|
|
|
|
struct mutex *fd_lock;
|
2020-10-08 07:27:42 +00:00
|
|
|
u32 pending_cnt;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
fd_lock = control_dev ? &hdev->fpriv_ctrl_list_lock : &hdev->fpriv_list_lock;
|
|
|
|
fd_list = control_dev ? &hdev->fpriv_ctrl_list : &hdev->fpriv_list;
|
2019-03-13 11:36:28 +00:00
|
|
|
|
2019-07-30 08:56:09 +00:00
|
|
|
/* Giving time for user to close FD, and for processes that are inside
|
|
|
|
* hl_device_open to finish
|
|
|
|
*/
|
2021-12-08 07:52:03 +00:00
|
|
|
if (!list_empty(fd_list))
|
2019-02-15 22:39:20 +00:00
|
|
|
ssleep(1);
|
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
if (timeout) {
|
|
|
|
pending_cnt = timeout;
|
|
|
|
} else {
|
|
|
|
if (hdev->process_kill_trial_cnt) {
|
|
|
|
/* Processes have been already killed */
|
|
|
|
pending_cnt = 1;
|
|
|
|
goto wait_for_processes;
|
|
|
|
} else {
|
|
|
|
/* Wait a small period after process kill */
|
|
|
|
pending_cnt = HL_PENDING_RESET_PER_SEC;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_lock(fd_lock);
|
2019-07-30 08:56:09 +00:00
|
|
|
|
|
|
|
/* This section must be protected because we are dereferencing
|
|
|
|
* pointers that are freed if the process exits
|
|
|
|
*/
|
2021-12-08 07:52:03 +00:00
|
|
|
list_for_each_entry(hpriv, fd_list, dev_node) {
|
2019-07-30 08:56:09 +00:00
|
|
|
task = get_pid_task(hpriv->taskpid, PIDTYPE_PID);
|
2019-02-15 22:39:20 +00:00
|
|
|
if (task) {
|
2019-07-30 06:10:50 +00:00
|
|
|
dev_info(hdev->dev, "Killing user process pid=%d\n",
|
|
|
|
task_pid_nr(task));
|
2019-02-15 22:39:20 +00:00
|
|
|
send_sig(SIGKILL, task, 1);
|
2019-07-30 08:56:09 +00:00
|
|
|
usleep_range(1000, 10000);
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
put_task_struct(task);
|
2021-07-03 08:50:32 +00:00
|
|
|
} else {
|
|
|
|
dev_warn(hdev->dev,
|
|
|
|
"Can't get task struct for PID so giving up on killing process\n");
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_unlock(fd_lock);
|
2021-07-03 08:50:32 +00:00
|
|
|
return -ETIME;
|
2019-02-15 22:39:20 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_unlock(fd_lock);
|
2019-07-30 08:56:09 +00:00
|
|
|
|
2020-10-31 20:03:55 +00:00
|
|
|
/*
|
|
|
|
* We killed the open users, but that doesn't mean they are closed.
|
|
|
|
* It could be that they are running a long cleanup phase in the driver
|
|
|
|
* e.g. MMU unmappings, or running other long teardown flow even before
|
|
|
|
* our cleanup.
|
|
|
|
* Therefore we need to wait again to make sure they are closed before
|
|
|
|
* continuing with the reset.
|
2019-04-06 10:23:54 +00:00
|
|
|
*/
|
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
wait_for_processes:
|
2021-12-08 07:52:03 +00:00
|
|
|
while ((!list_empty(fd_list)) && (pending_cnt)) {
|
2020-10-08 07:27:42 +00:00
|
|
|
dev_dbg(hdev->dev,
|
|
|
|
"Waiting for all unmap operations to finish before hard reset\n");
|
2019-03-13 11:36:28 +00:00
|
|
|
|
|
|
|
pending_cnt--;
|
|
|
|
|
|
|
|
ssleep(1);
|
|
|
|
}
|
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
/* All processes exited successfully */
|
2021-12-08 07:52:03 +00:00
|
|
|
if (list_empty(fd_list))
|
2020-10-08 07:27:42 +00:00
|
|
|
return 0;
|
2019-04-06 10:23:54 +00:00
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
/* Give up waiting for processes to exit */
|
|
|
|
if (hdev->process_kill_trial_cnt == HL_PENDING_RESET_MAX_TRIALS)
|
|
|
|
return -ETIME;
|
2019-04-06 10:23:54 +00:00
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
hdev->process_kill_trial_cnt++;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
return -EBUSY;
|
2019-02-15 22:39:20 +00:00
|
|
|
}
|
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
static void device_disable_open_processes(struct hl_device *hdev, bool control_dev)
|
2021-02-01 17:44:34 +00:00
|
|
|
{
|
2021-12-08 07:52:03 +00:00
|
|
|
struct list_head *fd_list;
|
2021-02-01 17:44:34 +00:00
|
|
|
struct hl_fpriv *hpriv;
|
2021-12-08 07:52:03 +00:00
|
|
|
struct mutex *fd_lock;
|
2021-02-01 17:44:34 +00:00
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
fd_lock = control_dev ? &hdev->fpriv_ctrl_list_lock : &hdev->fpriv_list_lock;
|
|
|
|
fd_list = control_dev ? &hdev->fpriv_ctrl_list : &hdev->fpriv_list;
|
|
|
|
|
|
|
|
mutex_lock(fd_lock);
|
|
|
|
list_for_each_entry(hpriv, fd_list, dev_node)
|
2021-02-01 17:44:34 +00:00
|
|
|
hpriv->hdev = NULL;
|
2021-12-08 07:52:03 +00:00
|
|
|
mutex_unlock(fd_lock);
|
2021-02-01 17:44:34 +00:00
|
|
|
}
|
|
|
|
|
2021-06-21 06:57:19 +00:00
|
|
|
static void handle_reset_trigger(struct hl_device *hdev, u32 flags)
|
|
|
|
{
|
|
|
|
u32 cur_reset_trigger = HL_RESET_TRIGGER_DEFAULT;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 'reset cause' is being updated here, because getting here
|
|
|
|
* means that it's the 1st time and the last time we're here
|
|
|
|
* ('in_reset' makes sure of it). This makes sure that
|
|
|
|
* 'reset_cause' will continue holding its 1st recorded reason!
|
|
|
|
*/
|
2021-09-16 11:00:38 +00:00
|
|
|
if (flags & HL_DRV_RESET_HEARTBEAT) {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_HEARTBEAT;
|
2021-09-16 11:00:38 +00:00
|
|
|
cur_reset_trigger = HL_DRV_RESET_HEARTBEAT;
|
|
|
|
} else if (flags & HL_DRV_RESET_TDR) {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_TDR;
|
2021-09-16 11:00:38 +00:00
|
|
|
cur_reset_trigger = HL_DRV_RESET_TDR;
|
|
|
|
} else if (flags & HL_DRV_RESET_FW_FATAL_ERR) {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
|
2021-09-16 11:00:38 +00:00
|
|
|
cur_reset_trigger = HL_DRV_RESET_FW_FATAL_ERR;
|
2021-06-21 06:57:19 +00:00
|
|
|
} else {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.curr_reset_cause = HL_RESET_CAUSE_UNKNOWN;
|
2021-06-21 06:57:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If reset cause is same twice, then reset_trigger_repeated
|
|
|
|
* is set and if this reset is due to a fatal FW error
|
|
|
|
* device is set to an unstable state.
|
|
|
|
*/
|
2021-11-23 13:15:22 +00:00
|
|
|
if (hdev->reset_info.prev_reset_trigger != cur_reset_trigger) {
|
|
|
|
hdev->reset_info.prev_reset_trigger = cur_reset_trigger;
|
|
|
|
hdev->reset_info.reset_trigger_repeated = 0;
|
2021-06-21 06:57:19 +00:00
|
|
|
} else {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.reset_trigger_repeated = 1;
|
2021-06-21 06:57:19 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* If reset is due to heartbeat, device CPU is no responsive in
|
|
|
|
* which case no point sending PCI disable message to it.
|
|
|
|
*
|
|
|
|
* If F/W is performing the reset, no need to send it a message to disable
|
|
|
|
* PCI access
|
|
|
|
*/
|
2021-09-16 11:00:38 +00:00
|
|
|
if ((flags & HL_DRV_RESET_HARD) &&
|
|
|
|
!(flags & (HL_DRV_RESET_HEARTBEAT | HL_DRV_RESET_BYPASS_REQ_TO_FW))) {
|
2021-06-21 06:57:19 +00:00
|
|
|
/* Disable PCI access from device F/W so he won't send
|
|
|
|
* us additional interrupts. We disable MSI/MSI-X at
|
|
|
|
* the halt_engines function and we can't have the F/W
|
|
|
|
* sending us interrupts after that. We need to disable
|
|
|
|
* the access here because if the device is marked
|
|
|
|
* disable, the message won't be send. Also, in case
|
|
|
|
* of heartbeat, the device CPU is marked as disable
|
|
|
|
* so this message won't be sent
|
|
|
|
*/
|
|
|
|
if (hl_fw_send_pci_access_msg(hdev,
|
|
|
|
CPUCP_PACKET_DISABLE_PCI_ACCESS))
|
|
|
|
dev_warn(hdev->dev,
|
|
|
|
"Failed to disable PCI access by F/W\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/*
|
|
|
|
* hl_device_reset - reset the device
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
2021-02-17 18:42:48 +00:00
|
|
|
* @flags: reset flags.
|
2019-02-15 22:39:20 +00:00
|
|
|
*
|
|
|
|
* Block future CS and wait for pending CS to be enqueued
|
|
|
|
* Call ASIC H/W fini
|
|
|
|
* Flush all completions
|
|
|
|
* Re-initialize all internal data structures
|
|
|
|
* Call ASIC H/W init, late_init
|
|
|
|
* Test queues
|
|
|
|
* Enable device
|
|
|
|
*
|
|
|
|
* Returns 0 for success or an error on failure.
|
|
|
|
*/
|
2021-02-17 18:42:48 +00:00
|
|
|
int hl_device_reset(struct hl_device *hdev, u32 flags)
|
2019-02-15 22:39:20 +00:00
|
|
|
{
|
2021-11-16 07:46:02 +00:00
|
|
|
bool hard_reset, from_hard_reset_thread, fw_reset, hard_instead_soft = false,
|
2022-02-17 14:15:26 +00:00
|
|
|
reset_upon_device_release = false, schedule_hard_reset = false,
|
2022-02-23 12:46:37 +00:00
|
|
|
skip_wq_flush, delay_reset;
|
2021-11-15 15:13:37 +00:00
|
|
|
u64 idle_mask[HL_BUSY_ENGINES_MASK_EXT_SIZE] = {0};
|
2021-11-30 21:02:21 +00:00
|
|
|
struct hl_ctx *ctx;
|
2019-02-15 22:39:20 +00:00
|
|
|
int i, rc;
|
|
|
|
|
|
|
|
if (!hdev->init_done) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "Can't reset before initialization is done\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2021-09-16 11:00:38 +00:00
|
|
|
hard_reset = !!(flags & HL_DRV_RESET_HARD);
|
|
|
|
from_hard_reset_thread = !!(flags & HL_DRV_RESET_FROM_RESET_THR);
|
|
|
|
fw_reset = !!(flags & HL_DRV_RESET_BYPASS_REQ_TO_FW);
|
2022-02-17 14:15:26 +00:00
|
|
|
skip_wq_flush = !!(flags & HL_DRV_RESET_DEV_RELEASE);
|
2022-02-23 12:46:37 +00:00
|
|
|
delay_reset = !!(flags & HL_DRV_RESET_DELAY);
|
2021-02-17 18:42:48 +00:00
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
if (!hard_reset && !hdev->asic_prop.supports_soft_reset) {
|
2021-06-08 14:24:52 +00:00
|
|
|
hard_instead_soft = true;
|
2020-05-18 13:48:01 +00:00
|
|
|
hard_reset = true;
|
|
|
|
}
|
|
|
|
|
2021-11-15 15:13:37 +00:00
|
|
|
if (hdev->reset_upon_device_release && (flags & HL_DRV_RESET_DEV_RELEASE)) {
|
|
|
|
if (hard_reset) {
|
|
|
|
dev_crit(hdev->dev,
|
|
|
|
"Aborting reset because hard-reset is mutually exclusive with reset-on-device-release\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2021-11-16 07:46:02 +00:00
|
|
|
reset_upon_device_release = true;
|
|
|
|
|
2021-06-08 14:24:52 +00:00
|
|
|
goto do_reset;
|
|
|
|
}
|
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
if (!hard_reset && !hdev->asic_prop.allow_inference_soft_reset) {
|
2021-06-08 14:24:52 +00:00
|
|
|
hard_instead_soft = true;
|
|
|
|
hard_reset = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hard_instead_soft)
|
|
|
|
dev_dbg(hdev->dev, "Doing hard-reset instead of soft-reset\n");
|
|
|
|
|
|
|
|
do_reset:
|
2020-10-08 07:27:42 +00:00
|
|
|
/* Re-entry of reset thread */
|
|
|
|
if (from_hard_reset_thread && hdev->process_kill_trial_cnt)
|
|
|
|
goto kill_processes;
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/*
|
|
|
|
* Prevent concurrency in this function - only one reset should be
|
|
|
|
* done at any given time. Only need to perform this if we didn't
|
|
|
|
* get from the dedicated hard reset thread
|
|
|
|
*/
|
|
|
|
if (!from_hard_reset_thread) {
|
|
|
|
/* Block future CS/VM/JOB completion operations */
|
2021-11-23 13:15:22 +00:00
|
|
|
spin_lock(&hdev->reset_info.lock);
|
|
|
|
if (hdev->reset_info.in_reset) {
|
2021-11-23 14:34:28 +00:00
|
|
|
/* We only allow scheduling of a hard reset during soft reset */
|
|
|
|
if (hard_reset && hdev->reset_info.is_in_soft_reset)
|
|
|
|
hdev->reset_info.hard_reset_schedule_flags = flags;
|
2021-11-23 13:15:22 +00:00
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
2019-02-15 22:39:20 +00:00
|
|
|
return 0;
|
2021-11-23 13:15:22 +00:00
|
|
|
}
|
|
|
|
hdev->reset_info.in_reset = 1;
|
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2022-02-23 12:46:37 +00:00
|
|
|
if (delay_reset)
|
|
|
|
usleep_range(HL_RESET_DELAY_USEC, HL_RESET_DELAY_USEC << 1);
|
|
|
|
|
2021-06-21 06:57:19 +00:00
|
|
|
handle_reset_trigger(hdev, flags);
|
2020-07-05 12:48:34 +00:00
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
/* This still allows the completion of some KDMA ops */
|
|
|
|
hdev->reset_info.is_in_soft_reset = !hard_reset;
|
2021-11-21 14:02:32 +00:00
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/* This also blocks future CS/VM/JOB completion operations */
|
|
|
|
hdev->disabled = true;
|
|
|
|
|
2021-07-01 07:09:28 +00:00
|
|
|
take_release_locks(hdev);
|
2019-07-30 08:56:09 +00:00
|
|
|
|
2021-09-30 08:53:37 +00:00
|
|
|
if (hard_reset)
|
|
|
|
dev_info(hdev->dev, "Going to reset device\n");
|
2021-11-16 07:46:02 +00:00
|
|
|
else if (reset_upon_device_release)
|
2022-04-02 19:09:16 +00:00
|
|
|
dev_dbg(hdev->dev, "Going to reset device after release by user\n");
|
2021-09-30 08:53:37 +00:00
|
|
|
else
|
2022-04-02 19:09:16 +00:00
|
|
|
dev_dbg(hdev->dev, "Going to reset engines of inference device\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
again:
|
|
|
|
if ((hard_reset) && (!from_hard_reset_thread)) {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.hard_reset_pending = true;
|
2019-04-06 12:41:35 +00:00
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
hdev->process_kill_trial_cnt = 0;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2021-11-22 10:29:22 +00:00
|
|
|
hdev->device_reset_work.flags = flags;
|
2021-08-09 19:43:37 +00:00
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/*
|
2021-05-04 17:10:47 +00:00
|
|
|
* Because the reset function can't run from heartbeat work,
|
|
|
|
* we need to call the reset function from a dedicated work.
|
2019-02-15 22:39:20 +00:00
|
|
|
*/
|
2020-10-08 07:27:42 +00:00
|
|
|
queue_delayed_work(hdev->device_reset_work.wq,
|
|
|
|
&hdev->device_reset_work.reset_work, 0);
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-02-17 14:15:26 +00:00
|
|
|
cleanup_resources(hdev, hard_reset, fw_reset, skip_wq_flush);
|
2021-01-12 16:37:19 +00:00
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
kill_processes:
|
2019-11-17 15:41:57 +00:00
|
|
|
if (hard_reset) {
|
|
|
|
/* Kill processes here after CS rollback. This is because the
|
|
|
|
* process can't really exit until all its CSs are done, which
|
|
|
|
* is what we do in cs rollback
|
|
|
|
*/
|
2021-12-08 07:52:03 +00:00
|
|
|
rc = device_kill_open_processes(hdev, 0, false);
|
2020-10-08 07:27:42 +00:00
|
|
|
|
|
|
|
if (rc == -EBUSY) {
|
|
|
|
if (hdev->device_fini_pending) {
|
|
|
|
dev_crit(hdev->dev,
|
|
|
|
"Failed to kill all open processes, stopping hard reset\n");
|
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* signal reset thread to reschedule */
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2020-05-18 19:27:46 +00:00
|
|
|
if (rc) {
|
|
|
|
dev_crit(hdev->dev,
|
|
|
|
"Failed to kill all open processes, stopping hard reset\n");
|
|
|
|
goto out_err;
|
|
|
|
}
|
2019-07-22 14:37:22 +00:00
|
|
|
|
2019-11-17 15:41:57 +00:00
|
|
|
/* Flush the Event queue workers to make sure no other thread is
|
|
|
|
* reading or writing to registers during the reset
|
|
|
|
*/
|
|
|
|
flush_workqueue(hdev->eq_wq);
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/* Reset the H/W. It will be in idle state after this returns */
|
2021-08-09 19:43:37 +00:00
|
|
|
hdev->asic_funcs->hw_fini(hdev, hard_reset, fw_reset);
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2019-02-15 22:39:22 +00:00
|
|
|
if (hard_reset) {
|
2021-10-21 08:24:41 +00:00
|
|
|
hdev->fw_loader.fw_comp_loaded = FW_TYPE_NONE;
|
2021-07-09 14:34:45 +00:00
|
|
|
|
2020-09-23 12:06:52 +00:00
|
|
|
/* Release kernel context */
|
2021-01-11 13:00:38 +00:00
|
|
|
if (hdev->kernel_ctx && hl_ctx_put(hdev->kernel_ctx) == 1)
|
2020-09-23 12:06:52 +00:00
|
|
|
hdev->kernel_ctx = NULL;
|
2021-07-09 14:34:45 +00:00
|
|
|
|
2019-02-15 22:39:22 +00:00
|
|
|
hl_vm_fini(hdev);
|
2019-05-29 11:43:04 +00:00
|
|
|
hl_mmu_fini(hdev);
|
2019-02-15 22:39:20 +00:00
|
|
|
hl_eq_reset(hdev, &hdev->event_queue);
|
2019-02-15 22:39:22 +00:00
|
|
|
}
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
/* Re-initialize PI,CI to 0 in all queues (hw queue, cq) */
|
|
|
|
hl_hw_queue_reset(hdev, hard_reset);
|
|
|
|
for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
|
|
|
|
hl_cq_reset(hdev, &hdev->completion_queue[i]);
|
|
|
|
|
2019-04-25 17:15:42 +00:00
|
|
|
/* Make sure the context switch phase will run again */
|
2021-11-30 21:02:21 +00:00
|
|
|
ctx = hl_get_compute_ctx(hdev);
|
|
|
|
if (ctx) {
|
|
|
|
atomic_set(&ctx->thread_ctx_switch_token, 1);
|
|
|
|
ctx->thread_ctx_switch_wait_token = 0;
|
|
|
|
hl_ctx_put(ctx);
|
2019-02-15 22:39:21 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/* Finished tear-down, starting to re-initialize */
|
|
|
|
|
|
|
|
if (hard_reset) {
|
2019-02-28 08:46:12 +00:00
|
|
|
hdev->device_cpu_disabled = false;
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.hard_reset_pending = false;
|
2019-02-28 08:46:12 +00:00
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
if (hdev->reset_info.reset_trigger_repeated &&
|
|
|
|
(hdev->reset_info.prev_reset_trigger ==
|
|
|
|
HL_DRV_RESET_FW_FATAL_ERR)) {
|
2021-06-21 06:57:19 +00:00
|
|
|
/* if there 2 back to back resets from FW,
|
|
|
|
* ensure driver puts the driver in a unusable state
|
|
|
|
*/
|
|
|
|
dev_crit(hdev->dev,
|
|
|
|
"Consecutive FW fatal errors received, stopping hard reset\n");
|
|
|
|
rc = -EIO;
|
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2019-03-17 07:12:29 +00:00
|
|
|
if (hdev->kernel_ctx) {
|
|
|
|
dev_crit(hdev->dev,
|
|
|
|
"kernel ctx was alive during hard reset, something is terribly wrong\n");
|
|
|
|
rc = -EBUSY;
|
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2019-05-29 11:43:04 +00:00
|
|
|
rc = hl_mmu_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed to initialize MMU S/W after hard reset\n");
|
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/* Allocate the kernel context */
|
|
|
|
hdev->kernel_ctx = kzalloc(sizeof(*hdev->kernel_ctx),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!hdev->kernel_ctx) {
|
|
|
|
rc = -ENOMEM;
|
2020-12-26 07:27:14 +00:00
|
|
|
hl_mmu_fini(hdev);
|
2019-02-15 22:39:20 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2021-11-30 21:08:21 +00:00
|
|
|
hdev->is_compute_ctx_active = false;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
rc = hl_ctx_init(hdev, hdev->kernel_ctx, true);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"failed to init kernel ctx in hard reset\n");
|
|
|
|
kfree(hdev->kernel_ctx);
|
|
|
|
hdev->kernel_ctx = NULL;
|
2020-12-26 07:27:14 +00:00
|
|
|
hl_mmu_fini(hdev);
|
2019-02-15 22:39:20 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-07-15 18:59:32 +00:00
|
|
|
/* Device is now enabled as part of the initialization requires
|
|
|
|
* communication with the device firmware to get information that
|
|
|
|
* is required for the initialization itself
|
|
|
|
*/
|
|
|
|
hdev->disabled = false;
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
rc = hdev->asic_funcs->hw_init(hdev);
|
|
|
|
if (rc) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "failed to initialize the H/W after reset\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2021-02-16 20:46:17 +00:00
|
|
|
/* If device is not idle fail the reset process */
|
|
|
|
if (!hdev->asic_funcs->is_device_idle(hdev, idle_mask,
|
|
|
|
HL_BUSY_ENGINES_MASK_EXT_SIZE, NULL)) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "device is not idle (mask 0x%llx_%llx) after reset\n",
|
2021-05-20 10:30:31 +00:00
|
|
|
idle_mask[1], idle_mask[0]);
|
2021-02-16 20:46:17 +00:00
|
|
|
rc = -EIO;
|
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/* Check that the communication with the device is working */
|
|
|
|
rc = hdev->asic_funcs->test_queues(hdev);
|
|
|
|
if (rc) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "Failed to detect if device is alive after reset\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hard_reset) {
|
|
|
|
rc = device_late_init(hdev);
|
|
|
|
if (rc) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "Failed late init after hard reset\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:22 +00:00
|
|
|
rc = hl_vm_init(hdev);
|
|
|
|
if (rc) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "Failed to init memory module after hard reset\n");
|
2019-02-15 22:39:22 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
|
2022-01-08 20:35:09 +00:00
|
|
|
hl_fw_set_max_power(hdev);
|
2019-02-15 22:39:20 +00:00
|
|
|
} else {
|
2021-11-16 07:59:32 +00:00
|
|
|
rc = hdev->asic_funcs->non_hard_reset_late_init(hdev);
|
2019-02-15 22:39:20 +00:00
|
|
|
if (rc) {
|
2021-11-16 07:46:02 +00:00
|
|
|
if (reset_upon_device_release)
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed late init in reset after device release\n");
|
|
|
|
else
|
|
|
|
dev_err(hdev->dev, "Failed late init after soft reset\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
goto out_err;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-11-23 14:34:28 +00:00
|
|
|
spin_lock(&hdev->reset_info.lock);
|
|
|
|
hdev->reset_info.is_in_soft_reset = false;
|
|
|
|
|
|
|
|
/* Schedule hard reset only if requested and if not already in hard reset.
|
|
|
|
* We keep 'in_reset' enabled, so no other reset can go in during the hard
|
|
|
|
* reset schedule
|
|
|
|
*/
|
|
|
|
if (!hard_reset && hdev->reset_info.hard_reset_schedule_flags)
|
|
|
|
schedule_hard_reset = true;
|
|
|
|
else
|
|
|
|
hdev->reset_info.in_reset = 0;
|
|
|
|
|
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.needs_reset = false;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2022-04-02 19:09:16 +00:00
|
|
|
if (hard_reset)
|
|
|
|
dev_info(hdev->dev, "Successfully finished resetting the device\n");
|
|
|
|
else
|
|
|
|
dev_dbg(hdev->dev, "Successfully finished resetting the device\n");
|
2021-02-01 19:23:43 +00:00
|
|
|
|
|
|
|
if (hard_reset) {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.hard_reset_cnt++;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2021-02-01 19:23:43 +00:00
|
|
|
/* After reset is done, we are ready to receive events from
|
|
|
|
* the F/W. We can't do it before because we will ignore events
|
|
|
|
* and if those events are fatal, we won't know about it and
|
|
|
|
* the device will be operational although it shouldn't be
|
|
|
|
*/
|
|
|
|
hdev->asic_funcs->enable_events_from_fw(hdev);
|
2021-11-16 07:46:02 +00:00
|
|
|
} else if (!reset_upon_device_release) {
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.soft_reset_cnt++;
|
2021-02-01 19:23:43 +00:00
|
|
|
}
|
2019-08-08 13:48:55 +00:00
|
|
|
|
2021-11-23 14:34:28 +00:00
|
|
|
if (schedule_hard_reset) {
|
|
|
|
dev_info(hdev->dev, "Performing hard reset scheduled during soft reset\n");
|
|
|
|
flags = hdev->reset_info.hard_reset_schedule_flags;
|
|
|
|
hdev->reset_info.hard_reset_schedule_flags = 0;
|
|
|
|
hdev->disabled = true;
|
|
|
|
hard_reset = true;
|
|
|
|
handle_reset_trigger(hdev, flags);
|
|
|
|
goto again;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_err:
|
|
|
|
hdev->disabled = true;
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.is_in_soft_reset = false;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
if (hard_reset) {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "Failed to reset! Device is NOT usable\n");
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.hard_reset_cnt++;
|
2021-11-16 07:46:02 +00:00
|
|
|
} else if (reset_upon_device_release) {
|
|
|
|
dev_err(hdev->dev, "Failed to reset device after user release\n");
|
2022-01-11 09:10:20 +00:00
|
|
|
flags |= HL_DRV_RESET_HARD;
|
|
|
|
flags &= ~HL_DRV_RESET_DEV_RELEASE;
|
2021-11-16 07:46:02 +00:00
|
|
|
hard_reset = true;
|
|
|
|
goto again;
|
2019-02-15 22:39:20 +00:00
|
|
|
} else {
|
2021-11-16 07:46:02 +00:00
|
|
|
dev_err(hdev->dev, "Failed to do soft-reset\n");
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.soft_reset_cnt++;
|
2022-01-11 09:10:20 +00:00
|
|
|
flags |= HL_DRV_RESET_HARD;
|
2019-02-15 22:39:20 +00:00
|
|
|
hard_reset = true;
|
|
|
|
goto again;
|
|
|
|
}
|
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.in_reset = 0;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/*
|
|
|
|
* hl_device_init - main initialization function for habanalabs device
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
* Allocate an id for the device, do early initialization and then call the
|
|
|
|
* ASIC specific initialization functions. Finally, create the cdev and the
|
|
|
|
* Linux device to expose it to the user
|
|
|
|
*/
|
|
|
|
int hl_device_init(struct hl_device *hdev, struct class *hclass)
|
|
|
|
{
|
2021-01-12 12:43:09 +00:00
|
|
|
int i, rc, cq_cnt, user_interrupt_cnt, cq_ready_cnt;
|
2019-07-30 06:10:02 +00:00
|
|
|
char *name;
|
2019-08-08 12:25:52 +00:00
|
|
|
bool add_cdev_sysfs_on_err = false;
|
2019-07-30 06:10:02 +00:00
|
|
|
|
2019-07-30 06:10:50 +00:00
|
|
|
name = kasprintf(GFP_KERNEL, "hl%d", hdev->id / 2);
|
2019-08-08 12:25:52 +00:00
|
|
|
if (!name) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
2019-02-15 22:39:11 +00:00
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
/* Initialize cdev and device structures */
|
|
|
|
rc = device_init_cdev(hdev, hclass, hdev->id, &hl_ops, name,
|
2019-07-30 06:10:02 +00:00
|
|
|
&hdev->cdev, &hdev->dev);
|
|
|
|
|
|
|
|
kfree(name);
|
2019-02-15 22:39:11 +00:00
|
|
|
|
|
|
|
if (rc)
|
|
|
|
goto out_disabled;
|
|
|
|
|
2019-07-30 06:10:50 +00:00
|
|
|
name = kasprintf(GFP_KERNEL, "hl_controlD%d", hdev->id / 2);
|
|
|
|
if (!name) {
|
|
|
|
rc = -ENOMEM;
|
2019-08-08 12:25:52 +00:00
|
|
|
goto free_dev;
|
2019-07-30 06:10:50 +00:00
|
|
|
}
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
/* Initialize cdev and device structures for control device */
|
|
|
|
rc = device_init_cdev(hdev, hclass, hdev->id_control, &hl_ctrl_ops,
|
2019-07-30 06:10:50 +00:00
|
|
|
name, &hdev->cdev_ctrl, &hdev->dev_ctrl);
|
|
|
|
|
|
|
|
kfree(name);
|
|
|
|
|
|
|
|
if (rc)
|
2019-08-08 12:25:52 +00:00
|
|
|
goto free_dev;
|
2019-07-30 06:10:50 +00:00
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/* Initialize ASIC function pointers and perform early init */
|
|
|
|
rc = device_early_init(hdev);
|
|
|
|
if (rc)
|
2019-08-08 12:25:52 +00:00
|
|
|
goto free_dev_ctrl;
|
2019-02-15 22:39:11 +00:00
|
|
|
|
2021-01-12 16:37:19 +00:00
|
|
|
user_interrupt_cnt = hdev->asic_prop.user_interrupt_count;
|
|
|
|
|
|
|
|
if (user_interrupt_cnt) {
|
|
|
|
hdev->user_interrupt = kcalloc(user_interrupt_cnt,
|
|
|
|
sizeof(*hdev->user_interrupt),
|
|
|
|
GFP_KERNEL);
|
|
|
|
|
|
|
|
if (!hdev->user_interrupt) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto early_fini;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
/*
|
|
|
|
* Start calling ASIC initialization. First S/W then H/W and finally
|
|
|
|
* late init
|
|
|
|
*/
|
|
|
|
rc = hdev->asic_funcs->sw_init(hdev);
|
|
|
|
if (rc)
|
2021-01-12 16:37:19 +00:00
|
|
|
goto user_interrupts_fini;
|
2019-02-15 22:39:13 +00:00
|
|
|
|
2021-06-14 19:18:41 +00:00
|
|
|
|
|
|
|
/* initialize completion structure for multi CS wait */
|
|
|
|
hl_multi_cs_completion_init(hdev);
|
|
|
|
|
2019-02-15 22:39:17 +00:00
|
|
|
/*
|
|
|
|
* Initialize the H/W queues. Must be done before hw_init, because
|
|
|
|
* there the addresses of the kernel queue are being written to the
|
|
|
|
* registers of the device
|
|
|
|
*/
|
|
|
|
rc = hl_hw_queues_create(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "failed to initialize kernel queues\n");
|
|
|
|
goto sw_fini;
|
|
|
|
}
|
|
|
|
|
2020-03-01 17:59:39 +00:00
|
|
|
cq_cnt = hdev->asic_prop.completion_queues_count;
|
|
|
|
|
2019-02-15 22:39:17 +00:00
|
|
|
/*
|
|
|
|
* Initialize the completion queues. Must be done before hw_init,
|
|
|
|
* because there the addresses of the completion queues are being
|
|
|
|
* passed as arguments to request_irq
|
|
|
|
*/
|
2020-06-24 11:49:43 +00:00
|
|
|
if (cq_cnt) {
|
|
|
|
hdev->completion_queue = kcalloc(cq_cnt,
|
|
|
|
sizeof(*hdev->completion_queue),
|
|
|
|
GFP_KERNEL);
|
2019-02-15 22:39:17 +00:00
|
|
|
|
2020-06-24 11:49:43 +00:00
|
|
|
if (!hdev->completion_queue) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"failed to allocate completion queues\n");
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto hw_queues_destroy;
|
|
|
|
}
|
2019-02-15 22:39:17 +00:00
|
|
|
}
|
|
|
|
|
2020-03-01 17:59:39 +00:00
|
|
|
for (i = 0, cq_ready_cnt = 0 ; i < cq_cnt ; i++, cq_ready_cnt++) {
|
|
|
|
rc = hl_cq_init(hdev, &hdev->completion_queue[i],
|
|
|
|
hdev->asic_funcs->get_queue_id_for_cq(hdev, i));
|
2019-02-15 22:39:17 +00:00
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"failed to initialize completion queue\n");
|
|
|
|
goto cq_fini;
|
|
|
|
}
|
2020-07-05 10:35:51 +00:00
|
|
|
hdev->completion_queue[i].cq_idx = i;
|
2019-02-15 22:39:17 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:18 +00:00
|
|
|
/*
|
|
|
|
* Initialize the event queue. Must be done before hw_init,
|
|
|
|
* because there the address of the event queue is being
|
|
|
|
* passed as argument to request_irq
|
|
|
|
*/
|
|
|
|
rc = hl_eq_init(hdev, &hdev->event_queue);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "failed to initialize event queue\n");
|
2021-01-12 16:37:19 +00:00
|
|
|
goto cq_fini;
|
2019-02-15 22:39:18 +00:00
|
|
|
}
|
|
|
|
|
2019-05-29 11:43:04 +00:00
|
|
|
/* MMU S/W must be initialized before kernel context is created */
|
|
|
|
rc = hl_mmu_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "Failed to initialize MMU S/W structures\n");
|
|
|
|
goto eq_fini;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:14 +00:00
|
|
|
/* Allocate the kernel context */
|
|
|
|
hdev->kernel_ctx = kzalloc(sizeof(*hdev->kernel_ctx), GFP_KERNEL);
|
|
|
|
if (!hdev->kernel_ctx) {
|
|
|
|
rc = -ENOMEM;
|
2019-05-29 11:43:04 +00:00
|
|
|
goto mmu_fini;
|
2019-02-15 22:39:14 +00:00
|
|
|
}
|
|
|
|
|
2021-11-30 21:08:21 +00:00
|
|
|
hdev->is_compute_ctx_active = false;
|
2019-02-15 22:39:14 +00:00
|
|
|
|
2021-06-06 07:28:51 +00:00
|
|
|
hdev->asic_funcs->state_dump_init(hdev);
|
|
|
|
|
2020-11-12 09:03:32 +00:00
|
|
|
hl_debugfs_add_device(hdev);
|
|
|
|
|
|
|
|
/* debugfs nodes are created in hl_ctx_init so it must be called after
|
|
|
|
* hl_debugfs_add_device.
|
|
|
|
*/
|
2019-02-15 22:39:14 +00:00
|
|
|
rc = hl_ctx_init(hdev, hdev->kernel_ctx, true);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "failed to initialize kernel context\n");
|
2019-08-01 13:57:36 +00:00
|
|
|
kfree(hdev->kernel_ctx);
|
2020-11-12 09:03:32 +00:00
|
|
|
goto remove_device_from_debugfs;
|
2019-02-15 22:39:14 +00:00
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:15 +00:00
|
|
|
rc = hl_cb_pool_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "failed to initialize CB pool\n");
|
|
|
|
goto release_ctx;
|
|
|
|
}
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
/*
|
2021-06-10 06:01:57 +00:00
|
|
|
* From this point, override rc (=0) in case of an error to allow
|
|
|
|
* debugging (by adding char devices and create sysfs nodes as part of
|
|
|
|
* the error flow).
|
2019-08-08 12:25:52 +00:00
|
|
|
*/
|
|
|
|
add_cdev_sysfs_on_err = true;
|
|
|
|
|
2020-07-15 18:59:32 +00:00
|
|
|
/* Device is now enabled as part of the initialization requires
|
|
|
|
* communication with the device firmware to get information that
|
|
|
|
* is required for the initialization itself
|
|
|
|
*/
|
|
|
|
hdev->disabled = false;
|
|
|
|
|
2019-02-15 22:39:16 +00:00
|
|
|
rc = hdev->asic_funcs->hw_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "failed to initialize the H/W\n");
|
|
|
|
rc = 0;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:17 +00:00
|
|
|
/* Check that the communication with the device is working */
|
|
|
|
rc = hdev->asic_funcs->test_queues(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "Failed to detect if device is alive\n");
|
|
|
|
rc = 0;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
rc = device_late_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "Failed late initialization\n");
|
|
|
|
rc = 0;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_info(hdev->dev, "Found %s device with %lluGB DRAM\n",
|
|
|
|
hdev->asic_name,
|
2021-06-03 10:18:20 +00:00
|
|
|
hdev->asic_prop.dram_size / SZ_1G);
|
2019-02-15 22:39:19 +00:00
|
|
|
|
2019-02-15 22:39:22 +00:00
|
|
|
rc = hl_vm_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "Failed to initialize memory module\n");
|
|
|
|
rc = 0;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
/*
|
2019-08-08 12:25:52 +00:00
|
|
|
* Expose devices and sysfs nodes to user.
|
|
|
|
* From here there is no need to add char devices and create sysfs nodes
|
|
|
|
* in case of an error.
|
|
|
|
*/
|
|
|
|
add_cdev_sysfs_on_err = false;
|
|
|
|
rc = device_cdev_sysfs_add(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"Failed to add char devices and sysfs nodes\n");
|
|
|
|
rc = 0;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
|
|
|
|
2020-08-08 20:34:47 +00:00
|
|
|
/* Need to call this again because the max power might change,
|
|
|
|
* depending on card type for certain ASICs
|
|
|
|
*/
|
2022-01-18 17:27:14 +00:00
|
|
|
if (hdev->asic_prop.set_max_power_on_device_init)
|
|
|
|
hl_fw_set_max_power(hdev);
|
2020-08-08 20:34:47 +00:00
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
/*
|
|
|
|
* hl_hwmon_init() must be called after device_late_init(), because only
|
2019-02-15 22:39:19 +00:00
|
|
|
* there we get the information from the device about which
|
2019-08-08 12:25:52 +00:00
|
|
|
* hwmon-related sensors the device supports.
|
|
|
|
* Furthermore, it must be done after adding the device to the system.
|
2019-02-15 22:39:19 +00:00
|
|
|
*/
|
|
|
|
rc = hl_hwmon_init(hdev);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(hdev->dev, "Failed to initialize hwmon\n");
|
|
|
|
rc = 0;
|
|
|
|
goto out_disabled;
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
dev_notice(hdev->dev,
|
|
|
|
"Successfully added device to habanalabs driver\n");
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
hdev->init_done = true;
|
|
|
|
|
2021-02-01 19:23:43 +00:00
|
|
|
/* After initialization is done, we are ready to receive events from
|
|
|
|
* the F/W. We can't do it before because we will ignore events and if
|
|
|
|
* those events are fatal, we won't know about it and the device will
|
|
|
|
* be operational although it shouldn't be
|
|
|
|
*/
|
|
|
|
hdev->asic_funcs->enable_events_from_fw(hdev);
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
return 0;
|
|
|
|
|
2019-02-15 22:39:15 +00:00
|
|
|
release_ctx:
|
|
|
|
if (hl_ctx_put(hdev->kernel_ctx) != 1)
|
|
|
|
dev_err(hdev->dev,
|
|
|
|
"kernel ctx is still alive on initialization failure\n");
|
2020-11-12 09:03:32 +00:00
|
|
|
remove_device_from_debugfs:
|
|
|
|
hl_debugfs_remove_device(hdev);
|
2019-05-29 11:43:04 +00:00
|
|
|
mmu_fini:
|
|
|
|
hl_mmu_fini(hdev);
|
2019-02-15 22:39:18 +00:00
|
|
|
eq_fini:
|
|
|
|
hl_eq_fini(hdev, &hdev->event_queue);
|
2019-02-15 22:39:17 +00:00
|
|
|
cq_fini:
|
|
|
|
for (i = 0 ; i < cq_ready_cnt ; i++)
|
|
|
|
hl_cq_fini(hdev, &hdev->completion_queue[i]);
|
|
|
|
kfree(hdev->completion_queue);
|
|
|
|
hw_queues_destroy:
|
|
|
|
hl_hw_queues_destroy(hdev);
|
2019-02-15 22:39:14 +00:00
|
|
|
sw_fini:
|
|
|
|
hdev->asic_funcs->sw_fini(hdev);
|
2021-01-12 16:37:19 +00:00
|
|
|
user_interrupts_fini:
|
|
|
|
kfree(hdev->user_interrupt);
|
2019-02-15 22:39:13 +00:00
|
|
|
early_fini:
|
|
|
|
device_early_fini(hdev);
|
2019-08-08 12:25:52 +00:00
|
|
|
free_dev_ctrl:
|
2020-11-29 07:34:12 +00:00
|
|
|
put_device(hdev->dev_ctrl);
|
2019-08-08 12:25:52 +00:00
|
|
|
free_dev:
|
2020-11-29 07:34:12 +00:00
|
|
|
put_device(hdev->dev);
|
2019-02-15 22:39:11 +00:00
|
|
|
out_disabled:
|
|
|
|
hdev->disabled = true;
|
2019-08-08 12:25:52 +00:00
|
|
|
if (add_cdev_sysfs_on_err)
|
|
|
|
device_cdev_sysfs_add(hdev);
|
2019-02-15 22:39:11 +00:00
|
|
|
if (hdev->pdev)
|
|
|
|
dev_err(&hdev->pdev->dev,
|
|
|
|
"Failed to initialize hl%d. Device is NOT usable !\n",
|
2019-09-01 13:13:25 +00:00
|
|
|
hdev->id / 2);
|
2019-02-15 22:39:11 +00:00
|
|
|
else
|
|
|
|
pr_err("Failed to initialize hl%d. Device is NOT usable !\n",
|
2019-09-01 13:13:25 +00:00
|
|
|
hdev->id / 2);
|
2019-02-15 22:39:11 +00:00
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_device_fini - main tear-down function for habanalabs device
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
*
|
|
|
|
* Destroy the device, call ASIC fini functions and release the id
|
|
|
|
*/
|
|
|
|
void hl_device_fini(struct hl_device *hdev)
|
|
|
|
{
|
2021-11-23 13:15:22 +00:00
|
|
|
bool device_in_reset;
|
2019-02-15 22:39:20 +00:00
|
|
|
ktime_t timeout;
|
2021-06-09 07:17:49 +00:00
|
|
|
u64 reset_sec;
|
2020-10-08 07:27:42 +00:00
|
|
|
int i, rc;
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
dev_info(hdev->dev, "Removing device\n");
|
|
|
|
|
2020-10-08 07:27:42 +00:00
|
|
|
hdev->device_fini_pending = 1;
|
|
|
|
flush_delayed_work(&hdev->device_reset_work.reset_work);
|
|
|
|
|
2021-06-09 07:17:49 +00:00
|
|
|
if (hdev->pldm)
|
|
|
|
reset_sec = HL_PLDM_HARD_RESET_MAX_TIMEOUT;
|
|
|
|
else
|
|
|
|
reset_sec = HL_HARD_RESET_MAX_TIMEOUT;
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
/*
|
|
|
|
* This function is competing with the reset function, so try to
|
|
|
|
* take the reset atomic and if we are already in middle of reset,
|
|
|
|
* wait until reset function is finished. Reset function is designed
|
2020-05-09 09:18:01 +00:00
|
|
|
* to always finish. However, in Gaudi, because of all the network
|
|
|
|
* ports, the hard reset could take between 10-30 seconds
|
2019-02-15 22:39:20 +00:00
|
|
|
*/
|
|
|
|
|
2021-06-09 07:17:49 +00:00
|
|
|
timeout = ktime_add_us(ktime_get(), reset_sec * 1000 * 1000);
|
2021-11-23 13:15:22 +00:00
|
|
|
|
|
|
|
spin_lock(&hdev->reset_info.lock);
|
|
|
|
device_in_reset = !!hdev->reset_info.in_reset;
|
|
|
|
if (!device_in_reset)
|
|
|
|
hdev->reset_info.in_reset = 1;
|
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
|
|
|
|
|
|
|
while (device_in_reset) {
|
2019-02-15 22:39:20 +00:00
|
|
|
usleep_range(50, 200);
|
2021-11-23 13:15:22 +00:00
|
|
|
|
|
|
|
spin_lock(&hdev->reset_info.lock);
|
|
|
|
device_in_reset = !!hdev->reset_info.in_reset;
|
|
|
|
if (!device_in_reset)
|
|
|
|
hdev->reset_info.in_reset = 1;
|
|
|
|
spin_unlock(&hdev->reset_info.lock);
|
|
|
|
|
2019-02-15 22:39:20 +00:00
|
|
|
if (ktime_compare(ktime_get(), timeout) > 0) {
|
2020-12-03 15:32:19 +00:00
|
|
|
dev_crit(hdev->dev,
|
|
|
|
"Failed to remove device because reset function did not finish\n");
|
2019-02-15 22:39:20 +00:00
|
|
|
return;
|
|
|
|
}
|
2019-04-02 12:46:02 +00:00
|
|
|
}
|
2019-02-15 22:39:20 +00:00
|
|
|
|
2021-01-18 19:39:46 +00:00
|
|
|
/* Disable PCI access from device F/W so it won't send us additional
|
|
|
|
* interrupts. We disable MSI/MSI-X at the halt_engines function and we
|
|
|
|
* can't have the F/W sending us interrupts after that. We need to
|
|
|
|
* disable the access here because if the device is marked disable, the
|
|
|
|
* message won't be send. Also, in case of heartbeat, the device CPU is
|
|
|
|
* marked as disable so this message won't be sent
|
|
|
|
*/
|
|
|
|
hl_fw_send_pci_access_msg(hdev, CPUCP_PACKET_DISABLE_PCI_ACCESS);
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
/* Mark device as disabled */
|
|
|
|
hdev->disabled = true;
|
|
|
|
|
2021-07-01 07:09:28 +00:00
|
|
|
take_release_locks(hdev);
|
2019-07-30 08:56:09 +00:00
|
|
|
|
2021-11-23 13:15:22 +00:00
|
|
|
hdev->reset_info.hard_reset_pending = true;
|
2019-04-06 12:41:35 +00:00
|
|
|
|
2019-02-15 22:39:19 +00:00
|
|
|
hl_hwmon_fini(hdev);
|
|
|
|
|
2022-02-17 14:15:26 +00:00
|
|
|
cleanup_resources(hdev, true, false, false);
|
2019-02-15 22:39:21 +00:00
|
|
|
|
2019-07-22 14:37:22 +00:00
|
|
|
/* Kill processes here after CS rollback. This is because the process
|
|
|
|
* can't really exit until all its CSs are done, which is what we
|
|
|
|
* do in cs rollback
|
|
|
|
*/
|
2020-10-08 07:27:42 +00:00
|
|
|
dev_info(hdev->dev,
|
|
|
|
"Waiting for all processes to exit (timeout of %u seconds)",
|
|
|
|
HL_PENDING_RESET_LONG_SEC);
|
|
|
|
|
2021-12-08 07:52:03 +00:00
|
|
|
rc = device_kill_open_processes(hdev, HL_PENDING_RESET_LONG_SEC, false);
|
2021-02-01 17:44:34 +00:00
|
|
|
if (rc) {
|
2020-05-18 19:27:46 +00:00
|
|
|
dev_crit(hdev->dev, "Failed to kill all open processes\n");
|
2021-12-08 07:52:03 +00:00
|
|
|
device_disable_open_processes(hdev, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = device_kill_open_processes(hdev, 0, true);
|
|
|
|
if (rc) {
|
|
|
|
dev_crit(hdev->dev, "Failed to kill all control device open processes\n");
|
|
|
|
device_disable_open_processes(hdev, true);
|
2021-02-01 17:44:34 +00:00
|
|
|
}
|
2019-07-22 14:37:22 +00:00
|
|
|
|
2019-02-15 22:39:15 +00:00
|
|
|
hl_cb_pool_fini(hdev);
|
|
|
|
|
2020-09-23 12:06:52 +00:00
|
|
|
/* Reset the H/W. It will be in idle state after this returns */
|
2021-08-09 19:43:37 +00:00
|
|
|
hdev->asic_funcs->hw_fini(hdev, true, false);
|
2020-09-23 12:06:52 +00:00
|
|
|
|
2021-10-21 08:24:41 +00:00
|
|
|
hdev->fw_loader.fw_comp_loaded = FW_TYPE_NONE;
|
2021-07-09 14:34:45 +00:00
|
|
|
|
2019-02-15 22:39:14 +00:00
|
|
|
/* Release kernel context */
|
|
|
|
if ((hdev->kernel_ctx) && (hl_ctx_put(hdev->kernel_ctx) != 1))
|
|
|
|
dev_err(hdev->dev, "kernel ctx is still alive\n");
|
|
|
|
|
2020-11-12 09:03:32 +00:00
|
|
|
hl_debugfs_remove_device(hdev);
|
|
|
|
|
2019-02-15 22:39:22 +00:00
|
|
|
hl_vm_fini(hdev);
|
|
|
|
|
2019-05-29 11:43:04 +00:00
|
|
|
hl_mmu_fini(hdev);
|
|
|
|
|
2019-02-15 22:39:18 +00:00
|
|
|
hl_eq_fini(hdev, &hdev->event_queue);
|
|
|
|
|
2019-02-15 22:39:17 +00:00
|
|
|
for (i = 0 ; i < hdev->asic_prop.completion_queues_count ; i++)
|
|
|
|
hl_cq_fini(hdev, &hdev->completion_queue[i]);
|
|
|
|
kfree(hdev->completion_queue);
|
2021-01-12 12:43:09 +00:00
|
|
|
kfree(hdev->user_interrupt);
|
2019-02-15 22:39:17 +00:00
|
|
|
|
|
|
|
hl_hw_queues_destroy(hdev);
|
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
/* Call ASIC S/W finalize function */
|
|
|
|
hdev->asic_funcs->sw_fini(hdev);
|
|
|
|
|
2019-02-15 22:39:11 +00:00
|
|
|
device_early_fini(hdev);
|
|
|
|
|
2019-08-08 12:25:52 +00:00
|
|
|
/* Hide devices and sysfs nodes from user */
|
|
|
|
device_cdev_sysfs_del(hdev);
|
2019-02-15 22:39:11 +00:00
|
|
|
|
|
|
|
pr_info("removed device successfully\n");
|
|
|
|
}
|
|
|
|
|
2019-02-15 22:39:13 +00:00
|
|
|
/*
|
|
|
|
* MMIO register access helper functions.
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_rreg - Read an MMIO register
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
* @reg: MMIO register offset (in bytes)
|
|
|
|
*
|
|
|
|
* Returns the value of the MMIO register we are asked to read
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
inline u32 hl_rreg(struct hl_device *hdev, u32 reg)
|
|
|
|
{
|
|
|
|
return readl(hdev->rmmio + reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* hl_wreg - Write to an MMIO register
|
|
|
|
*
|
|
|
|
* @hdev: pointer to habanalabs device structure
|
|
|
|
* @reg: MMIO register offset (in bytes)
|
|
|
|
* @val: 32-bit value
|
|
|
|
*
|
|
|
|
* Writes the 32-bit value into the MMIO register
|
|
|
|
*
|
|
|
|
*/
|
|
|
|
inline void hl_wreg(struct hl_device *hdev, u32 reg, u32 val)
|
|
|
|
{
|
|
|
|
writel(val, hdev->rmmio + reg);
|
|
|
|
}
|