2018-01-26 17:45:16 +00:00
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// SPDX-License-Identifier: GPL-2.0
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2005-04-16 22:20:36 +00:00
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/*
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* From setup-res.c, by:
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* Dave Rusling (david.rusling@reo.mts.dec.com)
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* David Mosberger (davidm@cs.arizona.edu)
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* David Miller (davem@redhat.com)
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* Ivan Kokshaysky (ink@jurassic.park.msu.ru)
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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PCI: move OF status = "disabled" detection to dev->match_driver
The blamed commit has broken probing on
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi when &enetc_port0
(PCI function 0) has status = "disabled".
Background: pci_scan_slot() has logic to say that if the function 0 of a
device is absent, the entire device is absent and we can skip the other
functions entirely. Traditionally, this has meant that
pci_bus_read_dev_vendor_id() returns an error code for that function.
However, since the blamed commit, there is an extra confounding
condition: function 0 of the device exists and has a valid vendor id,
but it is disabled in the device tree. In that case, pci_scan_slot()
would incorrectly skip the entire device instead of just that function.
In the case of NXP LS1028A, status = "disabled" does not mean that the
PCI function's config space is not available for reading. It is, but the
Ethernet port is just not functionally useful with a particular SerDes
protocol configuration (0x9999) due to pinmuxing constraints of the Soc.
So, pci_scan_slot() skips all other functions on the ENETC ECAM
(enetc_port1, enetc_port2, enetc_mdio_pf3 etc) when just enetc_port0 had
to not be probed.
There is an additional regression introduced by the change, caused by
its fundamental premise. The enetc driver needs to run code for all PCI
functions, regardless of whether they're enabled or not in the device
tree. That is no longer possible if the driver's probe function is no
longer called. But Rob recommends that we move the of_device_is_available()
detection to dev->match_driver, and this makes the PCI fixups still run
on all functions, while just probing drivers for those functions that
are enabled. So, a separate change in the enetc driver will have to move
the workarounds to a PCI fixup.
Fixes: 6fffbc7ae137 ("PCI: Honor firmware's device disabled status")
Link: https://lore.kernel.org/netdev/CAL_JsqLsVYiPLx2kcHkDQ4t=hQVCR7NHziDwi9cCFUFhx48Qow@mail.gmail.com/
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-08-03 13:58:56 +00:00
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#include <linux/of.h>
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2024-06-12 08:20:16 +00:00
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#include <linux/of_platform.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/proc_fs.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2005-04-16 22:20:36 +00:00
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#include "pci.h"
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2012-02-24 03:19:00 +00:00
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void pci_add_resource_offset(struct list_head *resources, struct resource *res,
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resource_size_t offset)
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2011-10-28 22:25:35 +00:00
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{
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2015-02-05 05:44:44 +00:00
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struct resource_entry *entry;
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2011-10-28 22:25:35 +00:00
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2015-02-05 05:44:44 +00:00
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entry = resource_list_create_entry(res, 0);
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if (!entry) {
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2019-04-20 04:03:46 +00:00
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pr_err("PCI: can't add host bridge window %pR\n", res);
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2011-10-28 22:25:35 +00:00
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return;
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}
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2015-02-05 05:44:44 +00:00
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entry->offset = offset;
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resource_list_add_tail(entry, resources);
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2012-02-24 03:19:00 +00:00
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}
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EXPORT_SYMBOL(pci_add_resource_offset);
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void pci_add_resource(struct list_head *resources, struct resource *res)
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{
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pci_add_resource_offset(resources, res, 0);
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2011-10-28 22:25:35 +00:00
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}
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EXPORT_SYMBOL(pci_add_resource);
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void pci_free_resource_list(struct list_head *resources)
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{
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2015-02-05 05:44:44 +00:00
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resource_list_free(resources);
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2011-10-28 22:25:35 +00:00
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}
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EXPORT_SYMBOL(pci_free_resource_list);
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2010-02-23 17:24:36 +00:00
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void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
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unsigned int flags)
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{
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struct pci_bus_resource *bus_res;
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bus_res = kzalloc(sizeof(struct pci_bus_resource), GFP_KERNEL);
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if (!bus_res) {
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dev_err(&bus->dev, "can't add %pR resource\n", res);
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return;
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}
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bus_res->res = res;
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bus_res->flags = flags;
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list_add_tail(&bus_res->list, &bus->resources);
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}
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struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n)
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{
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struct pci_bus_resource *bus_res;
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if (n < PCI_BRIDGE_RESOURCE_NUM)
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return bus->resource[n];
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n -= PCI_BRIDGE_RESOURCE_NUM;
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list_for_each_entry(bus_res, &bus->resources, list) {
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if (n-- == 0)
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return bus_res->res;
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}
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return NULL;
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}
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EXPORT_SYMBOL_GPL(pci_bus_resource_n);
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2023-03-06 15:10:11 +00:00
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void pci_bus_remove_resource(struct pci_bus *bus, struct resource *res)
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{
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struct pci_bus_resource *bus_res, *tmp;
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int i;
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for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
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if (bus->resource[i] == res) {
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bus->resource[i] = NULL;
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return;
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}
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}
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list_for_each_entry_safe(bus_res, tmp, &bus->resources, list) {
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if (bus_res->res == res) {
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list_del(&bus_res->list);
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kfree(bus_res);
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return;
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}
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}
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}
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2010-02-23 17:24:36 +00:00
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void pci_bus_remove_resources(struct pci_bus *bus)
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{
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int i;
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2012-09-15 00:48:41 +00:00
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struct pci_bus_resource *bus_res, *tmp;
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2010-02-23 17:24:36 +00:00
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for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
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2010-06-01 16:00:16 +00:00
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bus->resource[i] = NULL;
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2010-02-23 17:24:36 +00:00
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2012-09-15 00:48:41 +00:00
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list_for_each_entry_safe(bus_res, tmp, &bus->resources, list) {
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list_del(&bus_res->list);
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kfree(bus_res);
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}
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2010-02-23 17:24:36 +00:00
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}
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2016-05-28 23:09:16 +00:00
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int devm_request_pci_bus_resources(struct device *dev,
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struct list_head *resources)
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{
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struct resource_entry *win;
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struct resource *parent, *res;
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int err;
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resource_list_for_each_entry(win, resources) {
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res = win->res;
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switch (resource_type(res)) {
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case IORESOURCE_IO:
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parent = &ioport_resource;
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break;
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case IORESOURCE_MEM:
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parent = &iomem_resource;
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break;
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default:
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continue;
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}
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err = devm_request_resource(dev, parent, res);
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if (err)
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return err;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(devm_request_pci_bus_resources);
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PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
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static struct pci_bus_region pci_32_bit = {0, 0xffffffffULL};
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2018-04-03 14:40:54 +00:00
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
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static struct pci_bus_region pci_64_bit = {0,
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PCI: Add pci_bus_addr_t
David Ahern reported that d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
to fit in upstream windows") fails to boot on sparc/T5-8:
pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address 0x110204000)
The problem is that sparc64 assumed that dma_addr_t only needed to hold DMA
addresses, i.e., bus addresses returned via the DMA API (dma_map_single(),
etc.), while the PCI core assumed dma_addr_t could hold *any* bus address,
including raw BAR values. On sparc64, all DMA addresses fit in 32 bits, so
dma_addr_t is a 32-bit type. However, BAR values can be 64 bits wide, so
they don't fit in a dma_addr_t. d63e2e1f3df9 added new checking that
tripped over this mismatch.
Add pci_bus_addr_t, which is wide enough to hold any PCI bus address,
including both raw BAR values and DMA addresses. This will be 64 bits
on 64-bit platforms and on platforms with a 64-bit dma_addr_t. Then
dma_addr_t only needs to be wide enough to hold addresses from the DMA API.
[bhelgaas: changelog, bugzilla, Kconfig to ensure pci_bus_addr_t is at
least as wide as dma_addr_t, documentation]
Fixes: d63e2e1f3df9 ("sparc/PCI: Clip bridge windows to fit in upstream windows")
Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB")
Link: http://lkml.kernel.org/r/CAE9FiQU1gJY1LYrxs+ma5LCTEEe4xmtjRG0aXJ9K_Tsu+m9Wuw@mail.gmail.com
Link: http://lkml.kernel.org/r/1427857069-6789-1-git-send-email-yinghai@kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=96231
Reported-by: David Ahern <david.ahern@oracle.com>
Tested-by: David Ahern <david.ahern@oracle.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: David S. Miller <davem@davemloft.net>
CC: stable@vger.kernel.org # v3.19+
2015-05-28 00:23:51 +00:00
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(pci_bus_addr_t) 0xffffffffffffffffULL};
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static struct pci_bus_region pci_high = {(pci_bus_addr_t) 0x100000000ULL,
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(pci_bus_addr_t) 0xffffffffffffffffULL};
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PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
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#endif
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/*
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* @res contains CPU addresses. Clip it so the corresponding bus addresses
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* on @bus are entirely within @region. This is used to control the bus
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* addresses of resources we allocate, e.g., we may need a resource that
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* can be mapped by a 32-bit BAR.
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2005-04-16 22:20:36 +00:00
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*/
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PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
static void pci_clip_resource_to_region(struct pci_bus *bus,
|
|
|
|
struct resource *res,
|
|
|
|
struct pci_bus_region *region)
|
|
|
|
{
|
|
|
|
struct pci_bus_region r;
|
|
|
|
|
|
|
|
pcibios_resource_to_bus(bus, &r, res);
|
|
|
|
if (r.start < region->start)
|
|
|
|
r.start = region->start;
|
|
|
|
if (r.end > region->end)
|
|
|
|
r.end = region->end;
|
|
|
|
|
|
|
|
if (r.end < r.start)
|
|
|
|
res->end = res->start - 1;
|
|
|
|
else
|
|
|
|
pcibios_bus_to_resource(bus, res, &r);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_bus_alloc_from_region(struct pci_bus *bus, struct resource *res,
|
2006-06-13 00:06:02 +00:00
|
|
|
resource_size_t size, resource_size_t align,
|
2014-03-07 20:51:12 +00:00
|
|
|
resource_size_t min, unsigned long type_mask,
|
2024-05-07 10:25:19 +00:00
|
|
|
resource_alignf alignf,
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
void *alignf_data,
|
|
|
|
struct pci_bus_region *region)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
struct resource *r, avail;
|
|
|
|
resource_size_t max;
|
2023-04-04 15:45:25 +00:00
|
|
|
int ret;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2014-03-07 20:39:01 +00:00
|
|
|
type_mask |= IORESOURCE_TYPE_BITS;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2023-04-04 15:45:25 +00:00
|
|
|
pci_bus_for_each_resource(bus, r) {
|
2015-12-23 15:51:57 +00:00
|
|
|
resource_size_t min_used = min;
|
|
|
|
|
2010-12-16 17:38:36 +00:00
|
|
|
if (!r)
|
|
|
|
continue;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* type_mask must match */
|
|
|
|
if ((res->flags ^ r->flags) & type_mask)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* We cannot allocate a non-prefetching resource
|
|
|
|
from a pre-fetching area */
|
|
|
|
if ((r->flags & IORESOURCE_PREFETCH) &&
|
|
|
|
!(res->flags & IORESOURCE_PREFETCH))
|
|
|
|
continue;
|
|
|
|
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
avail = *r;
|
|
|
|
pci_clip_resource_to_region(bus, &avail, region);
|
|
|
|
|
2013-12-18 23:31:39 +00:00
|
|
|
/*
|
|
|
|
* "min" is typically PCIBIOS_MIN_IO or PCIBIOS_MIN_MEM to
|
|
|
|
* protect badly documented motherboard resources, but if
|
|
|
|
* this is an already-configured bridge window, its start
|
|
|
|
* overrides "min".
|
|
|
|
*/
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
if (avail.start)
|
2015-12-23 15:51:57 +00:00
|
|
|
min_used = avail.start;
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
|
|
|
|
max = avail.end;
|
2013-12-18 23:31:39 +00:00
|
|
|
|
2022-12-08 19:03:39 +00:00
|
|
|
/* Don't bother if available space isn't large enough */
|
|
|
|
if (size > max - min_used + 1)
|
|
|
|
continue;
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/* Ok, try it out.. */
|
2015-12-23 15:51:57 +00:00
|
|
|
ret = allocate_resource(r, res, size, min_used, max,
|
2013-12-18 23:31:39 +00:00
|
|
|
align, alignf, alignf_data);
|
2005-04-16 22:20:36 +00:00
|
|
|
if (ret == 0)
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
return 0;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_bus_alloc_resource - allocate a resource from a parent bus
|
|
|
|
* @bus: PCI bus
|
|
|
|
* @res: resource to allocate
|
|
|
|
* @size: size of resource to allocate
|
|
|
|
* @align: alignment of resource to allocate
|
|
|
|
* @min: minimum /proc/iomem address to allocate
|
|
|
|
* @type_mask: IORESOURCE_* type flags
|
|
|
|
* @alignf: resource alignment function
|
|
|
|
* @alignf_data: data argument for resource alignment function
|
|
|
|
*
|
|
|
|
* Given the PCI bus a device resides on, the size, minimum address,
|
|
|
|
* alignment and type, try to find an acceptable resource allocation
|
|
|
|
* for a specific device resource.
|
|
|
|
*/
|
2013-12-20 17:55:44 +00:00
|
|
|
int pci_bus_alloc_resource(struct pci_bus *bus, struct resource *res,
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
resource_size_t size, resource_size_t align,
|
2014-03-07 20:51:12 +00:00
|
|
|
resource_size_t min, unsigned long type_mask,
|
2024-05-07 10:25:19 +00:00
|
|
|
resource_alignf alignf,
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
void *alignf_data)
|
|
|
|
{
|
2018-04-03 14:40:54 +00:00
|
|
|
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
|
2013-12-20 17:55:44 +00:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (res->flags & IORESOURCE_MEM_64) {
|
|
|
|
rc = pci_bus_alloc_from_region(bus, res, size, align, min,
|
|
|
|
type_mask, alignf, alignf_data,
|
|
|
|
&pci_high);
|
|
|
|
if (rc == 0)
|
|
|
|
return 0;
|
|
|
|
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
return pci_bus_alloc_from_region(bus, res, size, align, min,
|
|
|
|
type_mask, alignf, alignf_data,
|
|
|
|
&pci_64_bit);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
PCI: Enforce bus address limits in resource allocation
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-20 16:57:37 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
return pci_bus_alloc_from_region(bus, res, size, align, min,
|
|
|
|
type_mask, alignf, alignf_data,
|
|
|
|
&pci_32_bit);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
2014-04-25 20:32:25 +00:00
|
|
|
EXPORT_SYMBOL(pci_bus_alloc_resource);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2015-01-15 22:21:49 +00:00
|
|
|
/*
|
|
|
|
* The @idx resource of @dev should be a PCI-PCI bridge window. If this
|
|
|
|
* resource fits inside a window of an upstream bridge, do nothing. If it
|
|
|
|
* overlaps an upstream window but extends outside it, clip the resource so
|
|
|
|
* it fits completely inside.
|
|
|
|
*/
|
|
|
|
bool pci_bus_clip_resource(struct pci_dev *dev, int idx)
|
|
|
|
{
|
|
|
|
struct pci_bus *bus = dev->bus;
|
|
|
|
struct resource *res = &dev->resource[idx];
|
|
|
|
struct resource orig_res = *res;
|
|
|
|
struct resource *r;
|
|
|
|
|
2023-04-04 15:45:25 +00:00
|
|
|
pci_bus_for_each_resource(bus, r) {
|
2015-01-15 22:21:49 +00:00
|
|
|
resource_size_t start, end;
|
|
|
|
|
|
|
|
if (!r)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (resource_type(res) != resource_type(r))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
start = max(r->start, res->start);
|
|
|
|
end = min(r->end, res->end);
|
|
|
|
|
|
|
|
if (start > end)
|
|
|
|
continue; /* no overlap */
|
|
|
|
|
|
|
|
if (res->start == start && res->end == end)
|
|
|
|
return false; /* no change */
|
|
|
|
|
|
|
|
res->start = start;
|
|
|
|
res->end = end;
|
2015-09-22 22:03:54 +00:00
|
|
|
res->flags &= ~IORESOURCE_UNSET;
|
|
|
|
orig_res.flags &= ~IORESOURCE_UNSET;
|
2019-04-20 04:07:20 +00:00
|
|
|
pci_info(dev, "%pR clipped to %pR\n", &orig_res, res);
|
2015-01-15 22:21:49 +00:00
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2012-11-04 04:39:31 +00:00
|
|
|
void __weak pcibios_resource_survey_bus(struct pci_bus *bus) { }
|
|
|
|
|
2016-03-03 23:53:04 +00:00
|
|
|
void __weak pcibios_bus_add_device(struct pci_dev *pdev) { }
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/**
|
2013-01-21 21:20:52 +00:00
|
|
|
* pci_bus_add_device - start driver for a single device
|
2005-04-16 22:20:36 +00:00
|
|
|
* @dev: device to add
|
|
|
|
*
|
2013-01-21 21:20:52 +00:00
|
|
|
* This adds add sysfs entries and start device drivers
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
2014-05-30 03:01:03 +00:00
|
|
|
void pci_bus_add_device(struct pci_dev *dev)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
PCI: move OF status = "disabled" detection to dev->match_driver
The blamed commit has broken probing on
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi when &enetc_port0
(PCI function 0) has status = "disabled".
Background: pci_scan_slot() has logic to say that if the function 0 of a
device is absent, the entire device is absent and we can skip the other
functions entirely. Traditionally, this has meant that
pci_bus_read_dev_vendor_id() returns an error code for that function.
However, since the blamed commit, there is an extra confounding
condition: function 0 of the device exists and has a valid vendor id,
but it is disabled in the device tree. In that case, pci_scan_slot()
would incorrectly skip the entire device instead of just that function.
In the case of NXP LS1028A, status = "disabled" does not mean that the
PCI function's config space is not available for reading. It is, but the
Ethernet port is just not functionally useful with a particular SerDes
protocol configuration (0x9999) due to pinmuxing constraints of the Soc.
So, pci_scan_slot() skips all other functions on the ENETC ECAM
(enetc_port1, enetc_port2, enetc_mdio_pf3 etc) when just enetc_port0 had
to not be probed.
There is an additional regression introduced by the change, caused by
its fundamental premise. The enetc driver needs to run code for all PCI
functions, regardless of whether they're enabled or not in the device
tree. That is no longer possible if the driver's probe function is no
longer called. But Rob recommends that we move the of_device_is_available()
detection to dev->match_driver, and this makes the PCI fixups still run
on all functions, while just probing drivers for those functions that
are enabled. So, a separate change in the enetc driver will have to move
the workarounds to a PCI fixup.
Fixes: 6fffbc7ae137 ("PCI: Honor firmware's device disabled status")
Link: https://lore.kernel.org/netdev/CAL_JsqLsVYiPLx2kcHkDQ4t=hQVCR7NHziDwi9cCFUFhx48Qow@mail.gmail.com/
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-08-03 13:58:56 +00:00
|
|
|
struct device_node *dn = dev->dev.of_node;
|
2006-08-28 18:43:25 +00:00
|
|
|
int retval;
|
2012-07-09 21:36:46 +00:00
|
|
|
|
2013-01-21 21:20:52 +00:00
|
|
|
/*
|
|
|
|
* Can not put in pci_device_add yet because resources
|
|
|
|
* are not assigned yet for some devices.
|
|
|
|
*/
|
2016-03-03 23:53:04 +00:00
|
|
|
pcibios_bus_add_device(dev);
|
2013-05-07 20:35:44 +00:00
|
|
|
pci_fixup_device(pci_fixup_final, dev);
|
PCI: Create device tree node for bridge
The PCI endpoint device such as Xilinx Alveo PCI card maps the register
spaces from multiple hardware peripherals to its PCI BAR. Normally,
the PCI core discovers devices and BARs using the PCI enumeration process.
There is no infrastructure to discover the hardware peripherals that are
present in a PCI device, and which can be accessed through the PCI BARs.
Apparently, the device tree framework requires a device tree node for the
PCI device. Thus, it can generate the device tree nodes for hardware
peripherals underneath. Because PCI is self discoverable bus, there might
not be a device tree node created for PCI devices. Furthermore, if the PCI
device is hot pluggable, when it is plugged in, the device tree nodes for
its parent bridges are required. Add support to generate device tree node
for PCI bridges.
Add an of_pci_make_dev_node() interface that can be used to create device
tree node for PCI devices.
Add a PCI_DYNAMIC_OF_NODES config option. When the option is turned on,
the kernel will generate device tree nodes for PCI bridges unconditionally.
Initially, add the basic properties for the dynamically generated device
tree nodes which include #address-cells, #size-cells, device_type,
compatible, ranges, reg.
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://lore.kernel.org/r/1692120000-46900-3-git-send-email-lizhi.hou@amd.com
Signed-off-by: Rob Herring <robh@kernel.org>
2023-08-15 17:19:57 +00:00
|
|
|
if (pci_is_bridge(dev))
|
|
|
|
of_pci_make_dev_node(dev);
|
2013-01-21 21:20:52 +00:00
|
|
|
pci_create_sysfs_dev_files(dev);
|
2013-11-30 22:40:28 +00:00
|
|
|
pci_proc_attach_device(dev);
|
2016-10-28 08:52:06 +00:00
|
|
|
pci_bridge_d3_update(dev);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
PCI: move OF status = "disabled" detection to dev->match_driver
The blamed commit has broken probing on
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi when &enetc_port0
(PCI function 0) has status = "disabled".
Background: pci_scan_slot() has logic to say that if the function 0 of a
device is absent, the entire device is absent and we can skip the other
functions entirely. Traditionally, this has meant that
pci_bus_read_dev_vendor_id() returns an error code for that function.
However, since the blamed commit, there is an extra confounding
condition: function 0 of the device exists and has a valid vendor id,
but it is disabled in the device tree. In that case, pci_scan_slot()
would incorrectly skip the entire device instead of just that function.
In the case of NXP LS1028A, status = "disabled" does not mean that the
PCI function's config space is not available for reading. It is, but the
Ethernet port is just not functionally useful with a particular SerDes
protocol configuration (0x9999) due to pinmuxing constraints of the Soc.
So, pci_scan_slot() skips all other functions on the ENETC ECAM
(enetc_port1, enetc_port2, enetc_mdio_pf3 etc) when just enetc_port0 had
to not be probed.
There is an additional regression introduced by the change, caused by
its fundamental premise. The enetc driver needs to run code for all PCI
functions, regardless of whether they're enabled or not in the device
tree. That is no longer possible if the driver's probe function is no
longer called. But Rob recommends that we move the of_device_is_available()
detection to dev->match_driver, and this makes the PCI fixups still run
on all functions, while just probing drivers for those functions that
are enabled. So, a separate change in the enetc driver will have to move
the workarounds to a PCI fixup.
Fixes: 6fffbc7ae137 ("PCI: Honor firmware's device disabled status")
Link: https://lore.kernel.org/netdev/CAL_JsqLsVYiPLx2kcHkDQ4t=hQVCR7NHziDwi9cCFUFhx48Qow@mail.gmail.com/
Suggested-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2023-08-03 13:58:56 +00:00
|
|
|
dev->match_driver = !dn || of_device_is_available(dn);
|
2013-01-21 21:20:51 +00:00
|
|
|
retval = device_attach(&dev->dev);
|
2020-07-06 23:32:40 +00:00
|
|
|
if (retval < 0 && retval != -EPROBE_DEFER)
|
2018-01-18 18:55:24 +00:00
|
|
|
pci_warn(dev, "device attach failed (%d)\n", retval);
|
2013-01-21 21:20:51 +00:00
|
|
|
|
2018-07-03 09:05:41 +00:00
|
|
|
pci_dev_assign_added(dev, true);
|
2024-06-12 08:20:16 +00:00
|
|
|
|
2024-07-17 04:27:46 +00:00
|
|
|
if (dev_of_node(&dev->dev) && pci_is_bridge(dev)) {
|
|
|
|
retval = of_platform_populate(dev_of_node(&dev->dev), NULL, NULL,
|
2024-06-12 08:20:16 +00:00
|
|
|
&dev->dev);
|
|
|
|
if (retval)
|
|
|
|
pci_err(dev, "failed to populate child OF nodes (%d)\n",
|
|
|
|
retval);
|
|
|
|
}
|
2008-11-21 18:42:35 +00:00
|
|
|
}
|
2014-04-25 20:32:25 +00:00
|
|
|
EXPORT_SYMBOL_GPL(pci_bus_add_device);
|
2008-11-21 18:42:35 +00:00
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
/**
|
2013-01-21 21:20:52 +00:00
|
|
|
* pci_bus_add_devices - start driver for PCI devices
|
2005-04-16 22:20:36 +00:00
|
|
|
* @bus: bus to check for new devices
|
|
|
|
*
|
2013-01-21 21:20:52 +00:00
|
|
|
* Start driver for PCI devices and add some sysfs entries.
|
2005-04-16 22:20:36 +00:00
|
|
|
*/
|
2009-02-03 23:45:26 +00:00
|
|
|
void pci_bus_add_devices(const struct pci_bus *bus)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
2008-11-21 18:41:45 +00:00
|
|
|
struct pci_bus *child;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
2008-02-14 22:56:56 +00:00
|
|
|
/* Skip already-added devices */
|
2018-07-03 09:05:41 +00:00
|
|
|
if (pci_dev_is_added(dev))
|
2005-04-16 22:20:36 +00:00
|
|
|
continue;
|
2014-05-30 03:01:03 +00:00
|
|
|
pci_bus_add_device(dev);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
list_for_each_entry(dev, &bus->devices, bus_list) {
|
2016-05-02 18:48:25 +00:00
|
|
|
/* Skip if device attach failed */
|
2018-07-03 09:05:41 +00:00
|
|
|
if (!pci_dev_is_added(dev))
|
2016-05-02 18:48:25 +00:00
|
|
|
continue;
|
2008-11-21 18:41:45 +00:00
|
|
|
child = dev->subordinate;
|
2013-04-12 05:44:16 +00:00
|
|
|
if (child)
|
|
|
|
pci_bus_add_devices(child);
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
}
|
2014-04-25 20:32:25 +00:00
|
|
|
EXPORT_SYMBOL(pci_bus_add_devices);
|
2005-04-16 22:20:36 +00:00
|
|
|
|
2024-01-30 10:02:43 +00:00
|
|
|
static void __pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
|
|
|
|
void *userdata, bool locked)
|
2005-08-18 04:33:01 +00:00
|
|
|
{
|
|
|
|
struct pci_dev *dev;
|
|
|
|
struct pci_bus *bus;
|
|
|
|
struct list_head *next;
|
2009-06-16 05:34:38 +00:00
|
|
|
int retval;
|
2005-08-18 04:33:01 +00:00
|
|
|
|
|
|
|
bus = top;
|
2024-01-30 10:02:43 +00:00
|
|
|
if (!locked)
|
|
|
|
down_read(&pci_bus_sem);
|
2005-08-18 04:33:01 +00:00
|
|
|
next = top->devices.next;
|
|
|
|
for (;;) {
|
|
|
|
if (next == &bus->devices) {
|
|
|
|
/* end of this bus, go up or finish */
|
|
|
|
if (bus == top)
|
|
|
|
break;
|
|
|
|
next = bus->self->bus_list.next;
|
|
|
|
bus = bus->self->bus;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
dev = list_entry(next, struct pci_dev, bus_list);
|
|
|
|
if (dev->subordinate) {
|
|
|
|
/* this is a pci-pci bridge, do its devices next */
|
|
|
|
next = dev->subordinate->devices.next;
|
|
|
|
bus = dev->subordinate;
|
|
|
|
} else
|
|
|
|
next = dev->bus_list.next;
|
|
|
|
|
2009-06-16 05:34:38 +00:00
|
|
|
retval = cb(dev, userdata);
|
|
|
|
if (retval)
|
|
|
|
break;
|
2005-08-18 04:33:01 +00:00
|
|
|
}
|
2024-01-30 10:02:43 +00:00
|
|
|
if (!locked)
|
|
|
|
up_read(&pci_bus_sem);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_walk_bus - walk devices on/under bus, calling callback.
|
|
|
|
* @top: bus whose devices should be walked
|
|
|
|
* @cb: callback to be called for each device found
|
|
|
|
* @userdata: arbitrary pointer to be passed to callback
|
|
|
|
*
|
|
|
|
* Walk the given bus, including any bridged devices
|
|
|
|
* on buses under this bus. Call the provided callback
|
|
|
|
* on each device found.
|
|
|
|
*
|
|
|
|
* We check the return of @cb each time. If it returns anything
|
|
|
|
* other than 0, we break out.
|
|
|
|
*/
|
|
|
|
void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), void *userdata)
|
|
|
|
{
|
|
|
|
__pci_walk_bus(top, cb, userdata, false);
|
2005-08-18 04:33:01 +00:00
|
|
|
}
|
2009-12-22 19:49:45 +00:00
|
|
|
EXPORT_SYMBOL_GPL(pci_walk_bus);
|
2005-08-18 04:33:01 +00:00
|
|
|
|
2024-01-30 10:02:43 +00:00
|
|
|
void pci_walk_bus_locked(struct pci_bus *top, int (*cb)(struct pci_dev *, void *), void *userdata)
|
|
|
|
{
|
|
|
|
lockdep_assert_held(&pci_bus_sem);
|
|
|
|
|
|
|
|
__pci_walk_bus(top, cb, userdata, true);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL_GPL(pci_walk_bus_locked);
|
|
|
|
|
2013-05-25 13:48:29 +00:00
|
|
|
struct pci_bus *pci_bus_get(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
if (bus)
|
|
|
|
get_device(&bus->dev);
|
|
|
|
return bus;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_bus_put(struct pci_bus *bus)
|
|
|
|
{
|
|
|
|
if (bus)
|
|
|
|
put_device(&bus->dev);
|
|
|
|
}
|