2014-09-20 23:46:05 +00:00
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/* Intel Ethernet Switch Host Interface Driver
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* Copyright(c) 2013 - 2014 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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* Contact Information:
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* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*/
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#ifndef _FM10K_H_
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#define _FM10K_H_
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#include <linux/types.h>
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#include <linux/etherdevice.h>
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#include <linux/rtnetlink.h>
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#include <linux/if_vlan.h>
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#include <linux/pci.h>
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2014-09-20 23:48:10 +00:00
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#include "fm10k_pf.h"
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#define FM10K_MAX_JUMBO_FRAME_SIZE 15358 /* Maximum supported size 15K */
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2014-09-20 23:49:03 +00:00
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#define MAX_QUEUES FM10K_MAX_QUEUES_PF
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#define FM10K_MIN_RXD 128
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#define FM10K_MAX_RXD 4096
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#define FM10K_DEFAULT_RXD 256
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#define FM10K_MIN_TXD 128
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#define FM10K_MAX_TXD 4096
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#define FM10K_DEFAULT_TXD 256
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#define FM10K_DEFAULT_TX_WORK 256
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#define FM10K_RXBUFFER_256 256
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#define FM10K_RXBUFFER_16384 16384
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#define FM10K_RX_HDR_LEN FM10K_RXBUFFER_256
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#if PAGE_SIZE <= FM10K_RXBUFFER_16384
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#define FM10K_RX_BUFSZ (PAGE_SIZE / 2)
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#else
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#define FM10K_RX_BUFSZ FM10K_RXBUFFER_16384
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#endif
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define FM10K_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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2014-09-20 23:51:15 +00:00
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#define FM10K_MAX_STATIONS 63
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struct fm10k_l2_accel {
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int size;
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u16 count;
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u16 dglort;
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struct rcu_head rcu;
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struct net_device *macvlan[0];
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};
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2014-09-20 23:49:03 +00:00
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enum fm10k_ring_state_t {
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__FM10K_TX_DETECT_HANG,
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__FM10K_HANG_CHECK_ARMED,
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};
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#define check_for_tx_hang(ring) \
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test_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
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#define set_check_for_tx_hang(ring) \
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set_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
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#define clear_check_for_tx_hang(ring) \
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clear_bit(__FM10K_TX_DETECT_HANG, &(ring)->state)
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struct fm10k_tx_buffer {
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struct fm10k_tx_desc *next_to_watch;
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struct sk_buff *skb;
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unsigned int bytecount;
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u16 gso_segs;
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u16 tx_flags;
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DEFINE_DMA_UNMAP_ADDR(dma);
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DEFINE_DMA_UNMAP_LEN(len);
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};
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struct fm10k_rx_buffer {
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dma_addr_t dma;
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struct page *page;
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u32 page_offset;
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};
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struct fm10k_queue_stats {
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u64 packets;
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u64 bytes;
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};
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struct fm10k_tx_queue_stats {
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u64 restart_queue;
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u64 csum_err;
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u64 tx_busy;
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u64 tx_done_old;
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};
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struct fm10k_rx_queue_stats {
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u64 alloc_failed;
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u64 csum_err;
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u64 errors;
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};
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struct fm10k_ring {
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struct fm10k_q_vector *q_vector;/* backpointer to host q_vector */
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struct net_device *netdev; /* netdev ring belongs to */
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struct device *dev; /* device for DMA mapping */
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2014-09-20 23:51:15 +00:00
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struct fm10k_l2_accel __rcu *l2_accel; /* L2 acceleration list */
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2014-09-20 23:49:03 +00:00
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void *desc; /* descriptor ring memory */
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union {
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struct fm10k_tx_buffer *tx_buffer;
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struct fm10k_rx_buffer *rx_buffer;
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};
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u32 __iomem *tail;
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unsigned long state;
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dma_addr_t dma; /* phys. address of descriptor ring */
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unsigned int size; /* length in bytes */
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u8 queue_index; /* needed for queue management */
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u8 reg_idx; /* holds the special value that gets
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* the hardware register offset
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* associated with this ring, which is
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* different for DCB and RSS modes
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*/
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u8 qos_pc; /* priority class of queue */
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u16 vid; /* default vlan ID of queue */
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u16 count; /* amount of descriptors */
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u16 next_to_alloc;
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u16 next_to_use;
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u16 next_to_clean;
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struct fm10k_queue_stats stats;
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struct u64_stats_sync syncp;
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union {
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/* Tx */
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struct fm10k_tx_queue_stats tx_stats;
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/* Rx */
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struct {
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struct fm10k_rx_queue_stats rx_stats;
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struct sk_buff *skb;
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};
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};
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} ____cacheline_internodealigned_in_smp;
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2014-09-20 23:48:51 +00:00
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struct fm10k_ring_container {
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2014-09-20 23:49:03 +00:00
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struct fm10k_ring *ring; /* pointer to linked list of rings */
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2014-09-20 23:48:51 +00:00
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unsigned int total_bytes; /* total bytes processed this int */
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unsigned int total_packets; /* total packets processed this int */
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u16 work_limit; /* total work allowed per interrupt */
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u16 itr; /* interrupt throttle rate value */
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u8 count; /* total number of rings in vector */
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};
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#define FM10K_ITR_MAX 0x0FFF /* maximum value for ITR */
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#define FM10K_ITR_10K 100 /* 100us */
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#define FM10K_ITR_20K 50 /* 50us */
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#define FM10K_ITR_ADAPTIVE 0x8000 /* adaptive interrupt moderation flag */
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#define FM10K_ITR_ENABLE (FM10K_ITR_AUTOMASK | FM10K_ITR_MASK_CLEAR)
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2014-09-20 23:49:03 +00:00
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static inline struct netdev_queue *txring_txq(const struct fm10k_ring *ring)
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{
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return &ring->netdev->_tx[ring->queue_index];
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}
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/* iterator for handling rings in ring container */
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#define fm10k_for_each_ring(pos, head) \
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for (pos = &(head).ring[(head).count]; (--pos) >= (head).ring;)
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2014-09-20 23:48:51 +00:00
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#define MAX_Q_VECTORS 256
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#define MIN_Q_VECTORS 1
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enum fm10k_non_q_vectors {
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FM10K_MBX_VECTOR,
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NON_Q_VECTORS_PF
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};
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#define NON_Q_VECTORS(hw) (((hw)->mac.type == fm10k_mac_pf) ? \
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NON_Q_VECTORS_PF : \
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0)
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#define MIN_MSIX_COUNT(hw) (MIN_Q_VECTORS + NON_Q_VECTORS(hw))
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struct fm10k_q_vector {
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struct fm10k_intfc *interface;
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u32 __iomem *itr; /* pointer to ITR register for this vector */
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u16 v_idx; /* index of q_vector within interface array */
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struct fm10k_ring_container rx, tx;
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struct napi_struct napi;
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char name[IFNAMSIZ + 9];
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struct rcu_head rcu; /* to avoid race with update stats on free */
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2014-09-20 23:49:03 +00:00
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/* for dynamic allocation of rings associated with this q_vector */
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struct fm10k_ring ring[0] ____cacheline_internodealigned_in_smp;
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2014-09-20 23:48:51 +00:00
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};
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2014-09-20 23:48:10 +00:00
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enum fm10k_ring_f_enum {
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RING_F_RSS,
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RING_F_QOS,
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RING_F_ARRAY_SIZE /* must be last in enum set */
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};
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struct fm10k_ring_feature {
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u16 limit; /* upper limit on feature indices */
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u16 indices; /* current value of indices */
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u16 mask; /* Mask used for feature to ring mapping */
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u16 offset; /* offset to start of feature */
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};
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#define fm10k_vxlan_port_for_each(vp, intfc) \
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list_for_each_entry(vp, &(intfc)->vxlan_port, list)
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struct fm10k_vxlan_port {
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struct list_head list;
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sa_family_t sa_family;
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__be16 port;
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};
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2014-09-20 23:46:45 +00:00
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struct fm10k_intfc {
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2014-09-20 23:48:10 +00:00
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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struct net_device *netdev;
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2014-09-20 23:51:15 +00:00
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struct fm10k_l2_accel *l2_accel; /* pointer to L2 acceleration list */
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2014-09-20 23:46:45 +00:00
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struct pci_dev *pdev;
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2014-09-20 23:48:10 +00:00
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unsigned long state;
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u32 flags;
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#define FM10K_FLAG_RESET_REQUESTED (u32)(1 << 0)
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#define FM10K_FLAG_RSS_FIELD_IPV4_UDP (u32)(1 << 1)
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#define FM10K_FLAG_RSS_FIELD_IPV6_UDP (u32)(1 << 2)
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#define FM10K_FLAG_RX_TS_ENABLED (u32)(1 << 3)
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#define FM10K_FLAG_SWPRI_CONFIG (u32)(1 << 4)
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int xcast_mode;
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2014-09-20 23:48:51 +00:00
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/* Tx fast path data */
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int num_tx_queues;
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u16 tx_itr;
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/* Rx fast path data */
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int num_rx_queues;
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u16 rx_itr;
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2014-09-20 23:49:03 +00:00
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/* TX */
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struct fm10k_ring *tx_ring[MAX_QUEUES] ____cacheline_aligned_in_smp;
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2014-09-20 23:49:25 +00:00
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u64 restart_queue;
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u64 tx_busy;
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u64 tx_csum_errors;
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u64 alloc_failed;
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u64 rx_csum_errors;
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u64 rx_errors;
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u64 tx_bytes_nic;
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u64 tx_packets_nic;
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u64 rx_bytes_nic;
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u64 rx_packets_nic;
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u64 rx_drops_nic;
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2014-09-20 23:48:10 +00:00
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u64 rx_overrun_pf;
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u64 rx_overrun_vf;
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2014-09-20 23:49:25 +00:00
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u32 tx_timeout_count;
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2014-09-20 23:46:45 +00:00
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2014-09-20 23:49:03 +00:00
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/* RX */
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struct fm10k_ring *rx_ring[MAX_QUEUES];
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2014-09-20 23:48:51 +00:00
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/* Queueing vectors */
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struct fm10k_q_vector *q_vector[MAX_Q_VECTORS];
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struct msix_entry *msix_entries;
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int num_q_vectors; /* current number of q_vectors for device */
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2014-09-20 23:48:10 +00:00
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struct fm10k_ring_feature ring_feature[RING_F_ARRAY_SIZE];
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struct fm10k_hw_stats stats;
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2014-09-20 23:46:45 +00:00
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struct fm10k_hw hw;
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u32 __iomem *uc_addr;
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2014-09-20 23:48:10 +00:00
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u16 msg_enable;
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2014-09-20 23:48:51 +00:00
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u16 tx_ring_count;
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u16 rx_ring_count;
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2014-09-20 23:49:25 +00:00
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struct timer_list service_timer;
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struct work_struct service_task;
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unsigned long next_stats_update;
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unsigned long next_tx_hang_check;
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unsigned long last_reset;
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unsigned long link_down_event;
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bool host_ready;
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2014-09-20 23:48:10 +00:00
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u32 reta[FM10K_RETA_SIZE];
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u32 rssrk[FM10K_RSSRK_SIZE];
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/* VXLAN port tracking information */
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struct list_head vxlan_port;
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#if defined(HAVE_DCBNL_IEEE) && defined(CONFIG_DCB)
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u8 pfc_en;
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#endif
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u8 rx_pause;
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/* GLORT resources in use by PF */
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u16 glort;
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u16 glort_count;
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/* VLAN ID for updating multicast/unicast lists */
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u16 vid;
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};
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enum fm10k_state_t {
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__FM10K_RESETTING,
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__FM10K_DOWN,
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2014-09-20 23:49:25 +00:00
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__FM10K_SERVICE_SCHED,
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__FM10K_SERVICE_DISABLE,
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2014-09-20 23:48:10 +00:00
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__FM10K_MBX_LOCK,
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__FM10K_LINK_DOWN,
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2014-09-20 23:46:45 +00:00
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};
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2014-09-20 23:46:05 +00:00
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2014-09-20 23:48:10 +00:00
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static inline void fm10k_mbx_lock(struct fm10k_intfc *interface)
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{
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/* busy loop if we cannot obtain the lock as some calls
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* such as ndo_set_rx_mode may be made in atomic context
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*/
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while (test_and_set_bit(__FM10K_MBX_LOCK, &interface->state))
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udelay(20);
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}
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static inline void fm10k_mbx_unlock(struct fm10k_intfc *interface)
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{
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/* flush memory to make sure state is correct */
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smp_mb__before_atomic();
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clear_bit(__FM10K_MBX_LOCK, &interface->state);
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}
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static inline int fm10k_mbx_trylock(struct fm10k_intfc *interface)
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{
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return !test_and_set_bit(__FM10K_MBX_LOCK, &interface->state);
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}
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|
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|
2014-09-20 23:49:03 +00:00
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|
/* fm10k_test_staterr - test bits in Rx descriptor status and error fields */
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static inline __le32 fm10k_test_staterr(union fm10k_rx_desc *rx_desc,
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|
|
const u32 stat_err_bits)
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|
|
|
{
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|
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|
return rx_desc->d.staterr & cpu_to_le32(stat_err_bits);
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|
|
|
}
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|
|
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|
|
|
/* fm10k_desc_unused - calculate if we have unused descriptors */
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|
|
static inline u16 fm10k_desc_unused(struct fm10k_ring *ring)
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|
|
|
{
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|
|
|
s16 unused = ring->next_to_clean - ring->next_to_use - 1;
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|
|
|
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|
return likely(unused < 0) ? unused + ring->count : unused;
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|
|
}
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|
|
#define FM10K_TX_DESC(R, i) \
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(&(((struct fm10k_tx_desc *)((R)->desc))[i]))
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|
|
#define FM10K_RX_DESC(R, i) \
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|
|
(&(((union fm10k_rx_desc *)((R)->desc))[i]))
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|
|
|
|
|
|
#define FM10K_MAX_TXD_PWR 14
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|
|
|
#define FM10K_MAX_DATA_PER_TXD (1 << FM10K_MAX_TXD_PWR)
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|
|
|
|
|
|
/* Tx Descriptors needed, worst case */
|
|
|
|
#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), FM10K_MAX_DATA_PER_TXD)
|
|
|
|
#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
|
|
|
|
|
|
|
|
enum fm10k_tx_flags {
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|
|
|
/* Tx offload flags */
|
|
|
|
FM10K_TX_FLAGS_CSUM = 0x01,
|
|
|
|
};
|
|
|
|
|
|
|
|
/* This structure is stored as little endian values as that is the native
|
|
|
|
* format of the Rx descriptor. The ordering of these fields is reversed
|
|
|
|
* from the actual ftag header to allow for a single bswap to take care
|
|
|
|
* of placing all of the values in network order
|
|
|
|
*/
|
|
|
|
union fm10k_ftag_info {
|
|
|
|
__le64 ftag;
|
|
|
|
struct {
|
|
|
|
/* dglort and sglort combined into a single 32bit desc read */
|
|
|
|
__le32 glort;
|
|
|
|
/* upper 16 bits of vlan are reserved 0 for swpri_type_user */
|
|
|
|
__le32 vlan;
|
|
|
|
} d;
|
|
|
|
struct {
|
|
|
|
__le16 dglort;
|
|
|
|
__le16 sglort;
|
|
|
|
__le16 vlan;
|
|
|
|
__le16 swpri_type_user;
|
|
|
|
} w;
|
|
|
|
};
|
|
|
|
|
|
|
|
struct fm10k_cb {
|
|
|
|
union fm10k_ftag_info fi;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define FM10K_CB(skb) ((struct fm10k_cb *)(skb)->cb)
|
|
|
|
|
2014-09-20 23:46:05 +00:00
|
|
|
/* main */
|
|
|
|
extern char fm10k_driver_name[];
|
|
|
|
extern const char fm10k_driver_version[];
|
2014-09-20 23:48:51 +00:00
|
|
|
int fm10k_init_queueing_scheme(struct fm10k_intfc *interface);
|
|
|
|
void fm10k_clear_queueing_scheme(struct fm10k_intfc *interface);
|
2014-09-20 23:50:03 +00:00
|
|
|
netdev_tx_t fm10k_xmit_frame_ring(struct sk_buff *skb,
|
|
|
|
struct fm10k_ring *tx_ring);
|
|
|
|
void fm10k_tx_timeout_reset(struct fm10k_intfc *interface);
|
|
|
|
bool fm10k_check_tx_hang(struct fm10k_ring *tx_ring);
|
|
|
|
void fm10k_alloc_rx_buffers(struct fm10k_ring *rx_ring, u16 cleaned_count);
|
2014-09-20 23:46:05 +00:00
|
|
|
|
|
|
|
/* PCI */
|
2014-09-20 23:48:51 +00:00
|
|
|
void fm10k_mbx_free_irq(struct fm10k_intfc *);
|
|
|
|
int fm10k_mbx_request_irq(struct fm10k_intfc *);
|
|
|
|
void fm10k_qv_free_irq(struct fm10k_intfc *interface);
|
|
|
|
int fm10k_qv_request_irq(struct fm10k_intfc *interface);
|
2014-09-20 23:46:05 +00:00
|
|
|
int fm10k_register_pci_driver(void);
|
|
|
|
void fm10k_unregister_pci_driver(void);
|
2014-09-20 23:48:29 +00:00
|
|
|
void fm10k_up(struct fm10k_intfc *interface);
|
|
|
|
void fm10k_down(struct fm10k_intfc *interface);
|
2014-09-20 23:49:25 +00:00
|
|
|
void fm10k_update_stats(struct fm10k_intfc *interface);
|
|
|
|
void fm10k_service_event_schedule(struct fm10k_intfc *interface);
|
|
|
|
void fm10k_update_rx_drop_en(struct fm10k_intfc *interface);
|
2014-09-20 23:48:10 +00:00
|
|
|
|
|
|
|
/* Netdev */
|
|
|
|
struct net_device *fm10k_alloc_netdev(void);
|
2014-09-20 23:49:43 +00:00
|
|
|
int fm10k_setup_rx_resources(struct fm10k_ring *);
|
|
|
|
int fm10k_setup_tx_resources(struct fm10k_ring *);
|
|
|
|
void fm10k_free_rx_resources(struct fm10k_ring *);
|
|
|
|
void fm10k_free_tx_resources(struct fm10k_ring *);
|
|
|
|
void fm10k_clean_all_rx_rings(struct fm10k_intfc *);
|
|
|
|
void fm10k_clean_all_tx_rings(struct fm10k_intfc *);
|
|
|
|
void fm10k_unmap_and_free_tx_resource(struct fm10k_ring *,
|
|
|
|
struct fm10k_tx_buffer *);
|
2014-09-20 23:48:20 +00:00
|
|
|
void fm10k_restore_rx_state(struct fm10k_intfc *);
|
|
|
|
void fm10k_reset_rx_state(struct fm10k_intfc *);
|
2014-09-20 23:50:42 +00:00
|
|
|
int fm10k_setup_tc(struct net_device *dev, u8 tc);
|
2014-09-20 23:48:29 +00:00
|
|
|
int fm10k_open(struct net_device *netdev);
|
|
|
|
int fm10k_close(struct net_device *netdev);
|
2014-09-20 23:50:15 +00:00
|
|
|
|
|
|
|
/* Ethtool */
|
|
|
|
void fm10k_set_ethtool_ops(struct net_device *dev);
|
2014-09-20 23:46:05 +00:00
|
|
|
#endif /* _FM10K_H_ */
|