2014-12-29 12:51:45 +00:00
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###
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# build: Generic definitions
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#
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# Lots of this code have been borrowed or heavily inspired from parts
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# of kbuild code, which is not credited, but mostly developed by:
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#
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# Copyright (C) Sam Ravnborg <sam@mars.ravnborg.org>, 2015
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# Copyright (C) Linus Torvalds <torvalds@linux-foundation.org>, 2015
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#
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###
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# Convenient variables
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comma := ,
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squote := '
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Kbuild: fix # escaping in .cmd files for future Make
I tried building using a freshly built Make (4.2.1-69-g8a731d1), but
already the objtool build broke with
orc_dump.c: In function ‘orc_dump’:
orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations]
if (elf_getshdrnum(elf, &nr_sections)) {
Turns out that with that new Make, the backslash was not removed, so cpp
didn't see a #include directive, grep found nothing, and
-DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS.
Now, that new Make behaviour is documented in their NEWS file:
* WARNING: Backward-incompatibility!
Number signs (#) appearing inside a macro reference or function invocation
no longer introduce comments and should not be escaped with backslashes:
thus a call such as:
foo := $(shell echo '#')
is legal. Previously the number sign needed to be escaped, for example:
foo := $(shell echo '\#')
Now this latter will resolve to "\#". If you want to write makefiles
portable to both versions, assign the number sign to a variable:
C := \#
foo := $(shell echo '$C')
This was claimed to be fixed in 3.81, but wasn't, for some reason.
To detect this change search for 'nocomment' in the .FEATURES variable.
This also fixes up the two make-cmd instances to replace # with $(pound)
rather than with \#. There might very well be other places that need
similar fixup in preparation for whatever future Make release contains
the above change, but at least this builds an x86_64 defconfig with the
new make.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
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pound := \#
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2014-12-29 12:51:45 +00:00
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###
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# Name of target with a '.' as filename prefix. foo/bar.o => foo/.bar.o
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dot-target = $(dir $@).$(notdir $@)
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###
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# filename of target with directory and extension stripped
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basetarget = $(basename $(notdir $@))
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###
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# The temporary file to save gcc -MD generated dependencies must not
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# contain a comma
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depfile = $(subst $(comma),_,$(dot-target).d)
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###
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# Check if both arguments has same arguments. Result is empty string if equal.
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arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
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$(filter-out $(cmd_$@), $(cmd_$(1))) )
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###
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# Escape single quote for use in echo statements
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escsq = $(subst $(squote),'\$(squote)',$1)
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# Echo command
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# Short version is used, if $(quiet) equals `quiet_', otherwise full one.
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echo-cmd = $(if $($(quiet)cmd_$(1)),\
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echo ' $(call escsq,$($(quiet)cmd_$(1)))';)
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###
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# Replace >$< with >$$< to preserve $ when reloading the .cmd file
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# (needed for make)
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Kbuild: fix # escaping in .cmd files for future Make
I tried building using a freshly built Make (4.2.1-69-g8a731d1), but
already the objtool build broke with
orc_dump.c: In function ‘orc_dump’:
orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations]
if (elf_getshdrnum(elf, &nr_sections)) {
Turns out that with that new Make, the backslash was not removed, so cpp
didn't see a #include directive, grep found nothing, and
-DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS.
Now, that new Make behaviour is documented in their NEWS file:
* WARNING: Backward-incompatibility!
Number signs (#) appearing inside a macro reference or function invocation
no longer introduce comments and should not be escaped with backslashes:
thus a call such as:
foo := $(shell echo '#')
is legal. Previously the number sign needed to be escaped, for example:
foo := $(shell echo '\#')
Now this latter will resolve to "\#". If you want to write makefiles
portable to both versions, assign the number sign to a variable:
C := \#
foo := $(shell echo '$C')
This was claimed to be fixed in 3.81, but wasn't, for some reason.
To detect this change search for 'nocomment' in the .FEATURES variable.
This also fixes up the two make-cmd instances to replace # with $(pound)
rather than with \#. There might very well be other places that need
similar fixup in preparation for whatever future Make release contains
the above change, but at least this builds an x86_64 defconfig with the
new make.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
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# Replace >#< with >$(pound)< to avoid starting a comment in the .cmd file
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2014-12-29 12:51:45 +00:00
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# (needed for make)
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# Replace >'< with >'\''< to be able to enclose the whole string in '...'
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# (needed for the shell)
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Kbuild: fix # escaping in .cmd files for future Make
I tried building using a freshly built Make (4.2.1-69-g8a731d1), but
already the objtool build broke with
orc_dump.c: In function ‘orc_dump’:
orc_dump.c:106:2: error: ‘elf_getshnum’ is deprecated [-Werror=deprecated-declarations]
if (elf_getshdrnum(elf, &nr_sections)) {
Turns out that with that new Make, the backslash was not removed, so cpp
didn't see a #include directive, grep found nothing, and
-DLIBELF_USE_DEPRECATED was wrongly put in CFLAGS.
Now, that new Make behaviour is documented in their NEWS file:
* WARNING: Backward-incompatibility!
Number signs (#) appearing inside a macro reference or function invocation
no longer introduce comments and should not be escaped with backslashes:
thus a call such as:
foo := $(shell echo '#')
is legal. Previously the number sign needed to be escaped, for example:
foo := $(shell echo '\#')
Now this latter will resolve to "\#". If you want to write makefiles
portable to both versions, assign the number sign to a variable:
C := \#
foo := $(shell echo '$C')
This was claimed to be fixed in 3.81, but wasn't, for some reason.
To detect this change search for 'nocomment' in the .FEATURES variable.
This also fixes up the two make-cmd instances to replace # with $(pound)
rather than with \#. There might very well be other places that need
similar fixup in preparation for whatever future Make release contains
the above change, but at least this builds an x86_64 defconfig with the
new make.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197847
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-04-08 21:35:28 +00:00
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make-cmd = $(call escsq,$(subst $(pound),$$(pound),$(subst $$,$$$$,$(cmd_$(1)))))
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2014-12-29 12:51:45 +00:00
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###
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# Find any prerequisites that is newer than target or that does not exist.
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# PHONY targets skipped in both cases.
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any-prereq = $(filter-out $(PHONY),$?) $(filter-out $(PHONY) $(wildcard $^),$^)
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2015-09-23 10:33:59 +00:00
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###
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# Copy dependency data into .cmd file
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# - gcc -M dependency info
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# - command line to create object 'cmd_object :='
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2015-09-23 10:34:00 +00:00
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dep-cmd = $(if $(wildcard $(fixdep)), \
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$(fixdep) $(depfile) $@ '$(make-cmd)' > $(dot-target).tmp; \
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rm -f $(depfile); \
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mv -f $(dot-target).tmp $(dot-target).cmd, \
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printf '\# cannot find fixdep (%s)\n' $(fixdep) > $(dot-target).cmd; \
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printf '\# using basic dep data\n\n' >> $(dot-target).cmd; \
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cat $(depfile) >> $(dot-target).cmd; \
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2016-12-04 20:42:52 +00:00
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printf '\n%s\n' 'cmd_$@ := $(make-cmd)' >> $(dot-target).cmd)
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2015-09-23 10:33:59 +00:00
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2014-12-29 12:51:45 +00:00
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###
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# if_changed_dep - execute command if any prerequisite is newer than
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# target, or command line has changed and update
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# dependencies in the cmd file
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if_changed_dep = $(if $(strip $(any-prereq) $(arg-check)), \
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2016-12-04 20:42:53 +00:00
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@set -e; \
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$(echo-cmd) $(cmd_$(1)) && $(dep-cmd))
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2014-12-29 12:51:45 +00:00
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# if_changed - execute command if any prerequisite is newer than
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# target, or command line has changed
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2016-12-04 20:42:53 +00:00
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if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
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@set -e; \
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$(echo-cmd) $(cmd_$(1)); \
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printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
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2014-12-29 12:51:45 +00:00
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###
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# C flags to be used in rule definitions, includes:
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# - depfile generation
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# - global $(CFLAGS)
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# - per target C flags
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# - per object C flags
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# - BUILD_STR macro to allow '-D"$(variable)"' constructs
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2016-11-28 02:43:46 +00:00
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c_flags_1 = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CFLAGS) -D"BUILD_STR(s)=\#s" $(CFLAGS_$(basetarget).o) $(CFLAGS_$(obj))
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2016-11-02 13:35:47 +00:00
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c_flags_2 = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(c_flags_1))
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c_flags = $(filter-out $(CFLAGS_REMOVE_$(obj)), $(c_flags_2))
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2016-11-28 02:43:46 +00:00
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cxx_flags = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CXXFLAGS) -D"BUILD_STR(s)=\#s" $(CXXFLAGS_$(basetarget).o) $(CXXFLAGS_$(obj))
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2016-09-27 14:18:46 +00:00
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###
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## HOSTCC C flags
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2016-11-28 02:43:46 +00:00
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host_c_flags = -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CHOSTFLAGS) -D"BUILD_STR(s)=\#s" $(CHOSTFLAGS_$(basetarget).o) $(CHOSTFLAGS_$(obj))
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