2007-04-30 06:30:56 +00:00
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#ifndef _ASM_POWERPC_PGTABLE_4K_H
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#define _ASM_POWERPC_PGTABLE_4K_H
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2005-11-07 00:06:55 +00:00
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/*
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* Entries per page directory level. The PTE level must use a 64b record
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* for each page table entry. The PMD and PGD level use a 32b record for
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* each entry by assuming that each entry is page aligned.
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*/
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#define PTE_INDEX_SIZE 9
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#define PMD_INDEX_SIZE 7
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#define PUD_INDEX_SIZE 7
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#define PGD_INDEX_SIZE 9
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2007-09-18 07:22:59 +00:00
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#ifndef __ASSEMBLY__
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2005-11-07 00:06:55 +00:00
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#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_INDEX_SIZE)
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#define PMD_TABLE_SIZE (sizeof(pmd_t) << PMD_INDEX_SIZE)
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#define PUD_TABLE_SIZE (sizeof(pud_t) << PUD_INDEX_SIZE)
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#define PGD_TABLE_SIZE (sizeof(pgd_t) << PGD_INDEX_SIZE)
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2007-09-18 07:22:59 +00:00
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#endif /* __ASSEMBLY__ */
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2005-11-07 00:06:55 +00:00
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#define PTRS_PER_PTE (1 << PTE_INDEX_SIZE)
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#define PTRS_PER_PMD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PUD (1 << PMD_INDEX_SIZE)
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#define PTRS_PER_PGD (1 << PGD_INDEX_SIZE)
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/* PMD_SHIFT determines what a second-level page table entry can map */
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#define PMD_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 08:57:52 +00:00
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/* With 4k base page size, hugepage PTEs go at the PMD level */
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#define MIN_HUGEPTE_SHIFT PMD_SHIFT
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2005-11-07 00:06:55 +00:00
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/* PUD_SHIFT determines what a third-level page table entry can map */
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#define PUD_SHIFT (PMD_SHIFT + PMD_INDEX_SIZE)
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#define PUD_SIZE (1UL << PUD_SHIFT)
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#define PUD_MASK (~(PUD_SIZE-1))
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/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
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#define PGDIR_SHIFT (PUD_SHIFT + PUD_INDEX_SIZE)
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/* PTE bits */
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2008-06-11 05:37:10 +00:00
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#define _PAGE_HASHPTE 0x0400 /* software: pte has an associated HPTE */
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2005-11-07 00:06:55 +00:00
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#define _PAGE_SECONDARY 0x8000 /* software: HPTE is in secondary group */
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#define _PAGE_GROUP_IX 0x7000 /* software: HPTE index within group */
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#define _PAGE_F_SECOND _PAGE_SECONDARY
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#define _PAGE_F_GIX _PAGE_GROUP_IX
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2008-07-28 03:28:03 +00:00
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#define _PAGE_SPECIAL 0x10000 /* software: special page */
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#define __HAVE_ARCH_PTE_SPECIAL
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2005-11-07 00:06:55 +00:00
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | \
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_PAGE_SECONDARY | _PAGE_GROUP_IX)
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2008-07-24 04:27:08 +00:00
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/* There is no 4K PFN hack on 4K pages */
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#define _PAGE_4K_PFN 0
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2005-11-07 00:06:55 +00:00
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/* PAGE_MASK gives the right answer below, but only by accident */
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/* It should be preserving the high 48 bits and then specifically */
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/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
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2009-02-12 12:18:46 +00:00
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_PAGE_HPTEFLAGS | _PAGE_SPECIAL)
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2005-11-07 00:06:55 +00:00
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/* Bits to mask out from a PMD to get to the PTE page */
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#define PMD_MASKED_BITS 0
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/* Bits to mask out from a PUD to get to the PMD page */
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#define PUD_MASKED_BITS 0
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/* Bits to mask out from a PGD to get to the PUD page */
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#define PGD_MASKED_BITS 0
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/* shift to put page number into pte */
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#define PTE_RPN_SHIFT (17)
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2006-02-20 03:05:56 +00:00
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#ifdef STRICT_MM_TYPECHECKS
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#define __real_pte(e,p) ((real_pte_t){(e)})
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#define __rpte_to_pte(r) ((r).pte)
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#else
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#define __real_pte(e,p) (e)
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#define __rpte_to_pte(r) (__pte(r))
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#endif
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#define __rpte_to_hidx(r,index) (pte_val(__rpte_to_pte(r)) >> 12)
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2005-11-07 00:06:55 +00:00
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#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
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do { \
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index = 0; \
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shift = mmu_psize_defs[psize].shift; \
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#define pte_iterate_hashed_end() } while(0)
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2007-05-08 06:27:28 +00:00
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#ifdef CONFIG_PPC_HAS_HASH_64K
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#define pte_pagesize_index(mm, addr, pte) get_slice_psize(mm, addr)
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#else
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#define pte_pagesize_index(mm, addr, pte) MMU_PAGE_4K
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#endif
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2006-06-15 00:45:18 +00:00
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2005-11-07 00:06:55 +00:00
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/*
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* 4-level page tables related bits
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*/
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#define pgd_none(pgd) (!pgd_val(pgd))
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#define pgd_bad(pgd) (pgd_val(pgd) == 0)
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#define pgd_present(pgd) (pgd_val(pgd) != 0)
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#define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0)
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2006-09-26 06:31:48 +00:00
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#define pgd_page_vaddr(pgd) (pgd_val(pgd) & ~PGD_MASKED_BITS)
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#define pgd_page(pgd) virt_to_page(pgd_page_vaddr(pgd))
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2005-11-07 00:06:55 +00:00
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#define pud_offset(pgdp, addr) \
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2006-09-26 06:31:48 +00:00
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(((pud_t *) pgd_page_vaddr(*(pgdp))) + \
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2005-11-07 00:06:55 +00:00
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(((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
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#define pud_ERROR(e) \
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2006-03-03 05:24:06 +00:00
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printk("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
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[POWERPC] Allow drivers to map individual 4k pages to userspace
Some drivers have resources that they want to be able to map into
userspace that are 4k in size. On a kernel configured with 64k pages
we currently end up mapping the 4k we want plus another 60k of
physical address space, which could contain anything. This can
introduce security problems, for example in the case of an infiniband
adaptor where the other 60k could contain registers that some other
program is using for its communications.
This patch adds a new function, remap_4k_pfn, which drivers can use to
map a single 4k page to userspace regardless of whether the kernel is
using a 4k or a 64k page size. Like remap_pfn_range, it would
typically be called in a driver's mmap function. It only maps a
single 4k page, which on a 64k page kernel appears replicated 16 times
throughout a 64k page. On a 4k page kernel it reduces to a call to
remap_pfn_range.
The way this works on a 64k kernel is that a new bit, _PAGE_4K_PFN,
gets set on the linux PTE. This alters the way that __hash_page_4K
computes the real address to put in the HPTE. The RPN field of the
linux PTE becomes the 4k RPN directly rather than being interpreted as
a 64k RPN. Since the RPN field is 32 bits, this means that physical
addresses being mapped with remap_4k_pfn have to be below 2^44,
i.e. 0x100000000000.
The patch also factors out the code in arch/powerpc/mm/hash_utils_64.c
that deals with demoting a process to use 4k pages into one function
that gets called in the various different places where we need to do
that. There were some discrepancies between exactly what was done in
the various places, such as a call to spu_flush_all_slbs in one case
but not in others.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-04-03 11:24:02 +00:00
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
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2007-04-30 06:30:56 +00:00
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#endif /* _ASM_POWERPC_PGTABLE_4K_H */
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