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89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
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/*
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* include/asm-v850/fpga85e2c.h -- Machine-dependent defs for
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* FPGA implementation of V850E2/NA85E2C
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*
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* Copyright (C) 2002,03 NEC Electronics Corporation
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* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#ifndef __V850_FPGA85E2C_H__
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#define __V850_FPGA85E2C_H__
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#include <asm/v850e2.h>
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#include <asm/clinkage.h>
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#define CPU_MODEL "v850e2/fpga85e2c"
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#define CPU_MODEL_LONG "NEC V850E2/NA85E2C"
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#define PLATFORM "fpga85e2c"
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#define PLATFORM_LONG "NA85E2C FPGA implementation"
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/* `external ram'. */
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#define ERAM_ADDR 0
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#define ERAM_SIZE 0x00100000 /* 1MB */
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/* FPGA specific control registers. */
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/* Writing a non-zero value to FLGREG(0) will signal the controlling CPU
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to stop execution. */
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#define FLGREG_ADDR(n) (0xFFE80100 + 2*(n))
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#define FLGREG(n) (*(volatile unsigned char *)FLGREG_ADDR (n))
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#define FLGREG_NUM 2
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#define CSDEV_ADDR(n) (0xFFE80110 + 2*(n))
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#define CSDEV(n) (*(volatile unsigned char *)CSDEV_ADDR (n))
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/* Timer interrupts 0-3, interrupt at intervals from CLK/4096 to CLK/16384. */
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#define IRQ_RPU(n) (60 + (n))
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#define IRQ_RPU_NUM 4
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/* For <asm/irq.h> */
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#define NUM_CPU_IRQS 64
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/* General-purpose timer. */
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/* control/status register (can only be read/written via bit insns) */
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#define RPU_GTMC_ADDR 0xFFFFFB00
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#define RPU_GTMC (*(volatile unsigned char *)RPU_GTMC_ADDR)
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#define RPU_GTMC_CE_BIT 7 /* clock enable (control) */
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#define RPU_GTMC_OV_BIT 6 /* overflow (status) */
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#define RPU_GTMC_CLK_BIT 1 /* 0 = .5 MHz CLK, 1 = 1 Mhz (control) */
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/* 32-bit count (8 least-significant bits are always zero). */
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#define RPU_GTM_ADDR 0xFFFFFB28
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#define RPU_GTM (*(volatile unsigned long *)RPU_GTMC_ADDR)
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/* For <asm/page.h> */
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#define PAGE_OFFSET ERAM_ADDR /* minimum allocatable address */
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/* For <asm/entry.h> */
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/* `R0 RAM', used for a few miscellaneous variables that must be accessible
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using a load instruction relative to R0. The FPGA implementation
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actually has no on-chip RAM, so we use part of main ram just after the
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interrupt vectors. */
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#ifdef __ASSEMBLY__
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#define R0_RAM_ADDR lo(C_SYMBOL_NAME(_r0_ram))
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#else
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extern char _r0_ram;
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#define R0_RAM_ADDR ((unsigned long)&_r0_ram);
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#endif
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/* For <asm/param.h> */
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#ifndef HZ
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#define HZ 122 /* actually, 8.192ms ticks =~ 122.07 */
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#endif
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#endif /* __V850_FPGA85E2C_H__ */
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