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243 lines
6.6 KiB
C
243 lines
6.6 KiB
C
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/*
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* arch/ppc64/kernel/ppc_asm.h
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*
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* Definitions used by various bits of low-level assembly code on PowerPC.
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*
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _PPC64_PPC_ASM_H
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#define _PPC64_PPC_ASM_H
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/*
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* Macros for storing registers into and loading registers from
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* exception frames.
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*/
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#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
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#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
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#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
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#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
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#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
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#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
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#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
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#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
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#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
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#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
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#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
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#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
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#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
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#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
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#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
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#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
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#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
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#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
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#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
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#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
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#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
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#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
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#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
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#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
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#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
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#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
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#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
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/* Macros to adjust thread priority for Iseries hardware multithreading */
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#define HMT_LOW or 1,1,1
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#define HMT_MEDIUM or 2,2,2
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#define HMT_HIGH or 3,3,3
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/* Insert the high 32 bits of the MSR into what will be the new
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MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
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bits. */
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#define FIX_SRR1(ra, rb) \
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mr rb,ra; \
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mfmsr ra; \
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rldimi ra,rb,0,32
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#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
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/*
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* LOADADDR( rn, name )
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* loads the address of 'name' into 'rn'
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*
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* LOADBASE( rn, name )
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* loads the address (less the low 16 bits) of 'name' into 'rn'
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* suitable for base+disp addressing
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*/
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#define LOADADDR(rn,name) \
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lis rn,name##@highest; \
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ori rn,rn,name##@higher; \
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rldicr rn,rn,32,31; \
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oris rn,rn,name##@h; \
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ori rn,rn,name##@l
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#define LOADBASE(rn,name) \
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lis rn,name@highest; \
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ori rn,rn,name@higher; \
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rldicr rn,rn,32,31; \
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oris rn,rn,name@ha
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#define SET_REG_TO_CONST(reg, value) \
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lis reg,(((value)>>48)&0xFFFF); \
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ori reg,reg,(((value)>>32)&0xFFFF); \
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rldicr reg,reg,32,31; \
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oris reg,reg,(((value)>>16)&0xFFFF); \
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ori reg,reg,((value)&0xFFFF);
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#define SET_REG_TO_LABEL(reg, label) \
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lis reg,(label)@highest; \
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ori reg,reg,(label)@higher; \
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rldicr reg,reg,32,31; \
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oris reg,reg,(label)@h; \
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ori reg,reg,(label)@l;
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/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
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* Then we can easily do this with one asm insn. -Peter
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*/
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#define tophys(rd,rs) \
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lis rd,((KERNELBASE>>48)&0xFFFF); \
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rldicr rd,rd,32,31; \
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sub rd,rs,rd
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#define tovirt(rd,rs) \
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lis rd,((KERNELBASE>>48)&0xFFFF); \
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rldicr rd,rd,32,31; \
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add rd,rs,rd
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/* Condition Register Bit Fields */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* General Purpose Registers (GPRs) */
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#define r0 0
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#define r1 1
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#define r2 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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/* Floating Point Registers (FPRs) */
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#define fr0 0
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#define fr1 1
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#define fr2 2
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#define fr3 3
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#define fr4 4
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#define fr5 5
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#define fr6 6
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#define fr7 7
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#define fr8 8
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#define fr9 9
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#define fr10 10
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#define fr11 11
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#define fr12 12
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#define fr13 13
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#define fr14 14
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#define fr15 15
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#define fr16 16
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#define fr17 17
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#define fr18 18
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#define fr19 19
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#define fr20 20
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#define fr21 21
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#define fr22 22
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#define fr23 23
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#define fr24 24
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#define fr25 25
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#define fr26 26
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#define fr27 27
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#define fr28 28
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#define fr29 29
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#define fr30 30
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#define fr31 31
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#define vr0 0
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#define vr1 1
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#define vr2 2
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#define vr3 3
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#define vr4 4
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#define vr5 5
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#define vr6 6
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#define vr7 7
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#define vr8 8
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#define vr9 9
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#define vr10 10
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#define vr11 11
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#define vr12 12
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#define vr13 13
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#define vr14 14
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#define vr15 15
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#define vr16 16
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#define vr17 17
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#define vr18 18
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#define vr19 19
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#define vr20 20
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#define vr21 21
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#define vr22 22
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#define vr23 23
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#define vr24 24
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#define vr25 25
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#define vr26 26
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#define vr27 27
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#define vr28 28
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#define vr29 29
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#define vr30 30
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#define vr31 31
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#endif /* _PPC64_PPC_ASM_H */
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