2018-09-27 07:48:08 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de>
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*/
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#include <linux/module.h>
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#include <linux/siox.h>
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#include <linux/gpio/driver.h>
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#include <linux/of.h>
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struct gpio_siox_ddata {
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struct gpio_chip gchip;
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struct mutex lock;
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u8 setdata[1];
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u8 getdata[3];
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2020-02-11 13:51:21 +00:00
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raw_spinlock_t irqlock;
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2018-09-27 07:48:08 +00:00
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u32 irq_enable;
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u32 irq_status;
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u32 irq_type[20];
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};
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/*
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* Note that this callback only sets the value that is clocked out in the next
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* cycle.
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*/
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static int gpio_siox_set_data(struct siox_device *sdevice, u8 status, u8 buf[])
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{
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struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
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mutex_lock(&ddata->lock);
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buf[0] = ddata->setdata[0];
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mutex_unlock(&ddata->lock);
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return 0;
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}
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static int gpio_siox_get_data(struct siox_device *sdevice, const u8 buf[])
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{
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struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev);
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size_t offset;
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u32 trigger;
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mutex_lock(&ddata->lock);
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2020-02-11 13:51:21 +00:00
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raw_spin_lock_irq(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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for (offset = 0; offset < 12; ++offset) {
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unsigned int bitpos = 11 - offset;
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unsigned int gpiolevel = buf[bitpos / 8] & (1 << bitpos % 8);
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unsigned int prev_level =
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ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
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u32 irq_type = ddata->irq_type[offset];
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if (gpiolevel) {
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if ((irq_type & IRQ_TYPE_LEVEL_HIGH) ||
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((irq_type & IRQ_TYPE_EDGE_RISING) && !prev_level))
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ddata->irq_status |= 1 << offset;
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} else {
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if ((irq_type & IRQ_TYPE_LEVEL_LOW) ||
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((irq_type & IRQ_TYPE_EDGE_FALLING) && prev_level))
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ddata->irq_status |= 1 << offset;
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}
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}
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trigger = ddata->irq_status & ddata->irq_enable;
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2020-02-11 13:51:21 +00:00
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raw_spin_unlock_irq(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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ddata->getdata[0] = buf[0];
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ddata->getdata[1] = buf[1];
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ddata->getdata[2] = buf[2];
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mutex_unlock(&ddata->lock);
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for (offset = 0; offset < 12; ++offset) {
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if (trigger & (1 << offset)) {
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struct irq_domain *irqdomain = ddata->gchip.irq.domain;
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unsigned int irq = irq_find_mapping(irqdomain, offset);
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/*
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* Conceptually handle_nested_irq should call the flow
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* handler of the irq chip. But it doesn't, so we have
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* to clean the irq_status here.
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*/
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2020-02-11 13:51:21 +00:00
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raw_spin_lock_irq(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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ddata->irq_status &= ~(1 << offset);
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2020-02-11 13:51:21 +00:00
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raw_spin_unlock_irq(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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handle_nested_irq(irq);
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}
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}
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return 0;
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}
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static void gpio_siox_irq_ack(struct irq_data *d)
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{
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2023-03-20 09:55:09 +00:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
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2018-09-27 07:48:08 +00:00
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2020-02-11 13:51:21 +00:00
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raw_spin_lock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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ddata->irq_status &= ~(1 << d->hwirq);
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2020-02-11 13:51:21 +00:00
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raw_spin_unlock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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}
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static void gpio_siox_irq_mask(struct irq_data *d)
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{
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2023-03-20 09:55:09 +00:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
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2018-09-27 07:48:08 +00:00
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2020-02-11 13:51:21 +00:00
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raw_spin_lock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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ddata->irq_enable &= ~(1 << d->hwirq);
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2020-02-11 13:51:21 +00:00
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raw_spin_unlock(&ddata->irqlock);
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2023-03-20 09:55:09 +00:00
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gpiochip_disable_irq(gc, irqd_to_hwirq(d));
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2018-09-27 07:48:08 +00:00
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}
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static void gpio_siox_irq_unmask(struct irq_data *d)
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{
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2023-03-20 09:55:09 +00:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
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2018-09-27 07:48:08 +00:00
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2023-03-20 09:55:09 +00:00
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gpiochip_enable_irq(gc, irqd_to_hwirq(d));
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2020-02-11 13:51:21 +00:00
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raw_spin_lock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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ddata->irq_enable |= 1 << d->hwirq;
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2020-02-11 13:51:21 +00:00
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raw_spin_unlock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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}
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static int gpio_siox_irq_set_type(struct irq_data *d, u32 type)
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{
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2023-03-20 09:55:09 +00:00
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct gpio_siox_ddata *ddata = gpiochip_get_data(gc);
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2018-09-27 07:48:08 +00:00
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2020-02-11 13:51:21 +00:00
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raw_spin_lock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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ddata->irq_type[d->hwirq] = type;
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2020-02-11 13:51:21 +00:00
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raw_spin_unlock(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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return 0;
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}
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static int gpio_siox_get(struct gpio_chip *chip, unsigned int offset)
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{
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2023-03-20 09:55:09 +00:00
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struct gpio_siox_ddata *ddata = gpiochip_get_data(chip);
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2018-09-27 07:48:08 +00:00
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int ret;
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mutex_lock(&ddata->lock);
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if (offset >= 12) {
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unsigned int bitpos = 19 - offset;
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ret = ddata->setdata[0] & (1 << bitpos);
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} else {
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unsigned int bitpos = 11 - offset;
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ret = ddata->getdata[bitpos / 8] & (1 << (bitpos % 8));
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}
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mutex_unlock(&ddata->lock);
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return ret;
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}
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static void gpio_siox_set(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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2023-03-20 09:55:09 +00:00
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struct gpio_siox_ddata *ddata = gpiochip_get_data(chip);
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2018-09-27 07:48:08 +00:00
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u8 mask = 1 << (19 - offset);
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mutex_lock(&ddata->lock);
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if (value)
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ddata->setdata[0] |= mask;
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else
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ddata->setdata[0] &= ~mask;
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mutex_unlock(&ddata->lock);
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}
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static int gpio_siox_direction_input(struct gpio_chip *chip,
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unsigned int offset)
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{
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if (offset >= 12)
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return -EINVAL;
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return 0;
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}
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static int gpio_siox_direction_output(struct gpio_chip *chip,
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unsigned int offset, int value)
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{
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if (offset < 12)
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return -EINVAL;
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gpio_siox_set(chip, offset, value);
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return 0;
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}
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static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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if (offset < 12)
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2019-11-06 08:54:12 +00:00
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return GPIO_LINE_DIRECTION_IN;
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2018-09-27 07:48:08 +00:00
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else
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2019-11-06 08:54:12 +00:00
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return GPIO_LINE_DIRECTION_OUT;
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2018-09-27 07:48:08 +00:00
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}
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2023-03-20 09:55:09 +00:00
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static const struct irq_chip gpio_siox_irq_chip = {
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.name = "siox-gpio",
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.irq_ack = gpio_siox_irq_ack,
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.irq_mask = gpio_siox_irq_mask,
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.irq_unmask = gpio_siox_irq_unmask,
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.irq_set_type = gpio_siox_irq_set_type,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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2018-09-27 07:48:08 +00:00
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static int gpio_siox_probe(struct siox_device *sdevice)
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{
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struct gpio_siox_ddata *ddata;
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2019-06-25 10:36:12 +00:00
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struct gpio_irq_chip *girq;
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2019-06-26 08:21:27 +00:00
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struct device *dev = &sdevice->dev;
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2023-03-20 09:55:09 +00:00
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struct gpio_chip *gc;
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2018-09-27 07:48:08 +00:00
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int ret;
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2019-06-26 08:21:27 +00:00
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ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
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2018-09-27 07:48:08 +00:00
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if (!ddata)
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return -ENOMEM;
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2019-06-26 08:21:27 +00:00
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dev_set_drvdata(dev, ddata);
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2018-09-27 07:48:08 +00:00
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mutex_init(&ddata->lock);
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2020-02-11 13:51:21 +00:00
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raw_spin_lock_init(&ddata->irqlock);
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2018-09-27 07:48:08 +00:00
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2023-03-20 09:55:09 +00:00
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gc = &ddata->gchip;
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gc->base = -1;
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gc->can_sleep = 1;
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gc->parent = dev;
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gc->owner = THIS_MODULE;
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gc->get = gpio_siox_get;
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gc->set = gpio_siox_set;
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gc->direction_input = gpio_siox_direction_input;
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gc->direction_output = gpio_siox_direction_output;
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gc->get_direction = gpio_siox_get_direction;
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gc->ngpio = 20;
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girq = &gc->irq;
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gpio_irq_chip_set_chip(girq, &gpio_siox_irq_chip);
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2019-06-25 10:36:12 +00:00
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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2020-09-07 15:31:35 +00:00
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girq->threaded = true;
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2018-09-27 07:48:08 +00:00
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2023-03-20 09:55:09 +00:00
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ret = devm_gpiochip_add_data(dev, gc, ddata);
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2019-06-26 08:09:00 +00:00
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if (ret)
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2019-06-26 08:21:27 +00:00
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dev_err(dev, "Failed to register gpio chip (%d)\n", ret);
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2018-09-27 07:48:08 +00:00
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return ret;
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}
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static struct siox_driver gpio_siox_driver = {
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.probe = gpio_siox_probe,
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.set_data = gpio_siox_set_data,
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.get_data = gpio_siox_get_data,
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.driver = {
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.name = "gpio-siox",
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},
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};
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2019-06-24 05:40:34 +00:00
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module_siox_driver(gpio_siox_driver);
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2018-09-27 07:48:08 +00:00
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MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
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MODULE_DESCRIPTION("SIOX gpio driver");
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MODULE_LICENSE("GPL v2");
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